公开(公告)号：US09761489B2

公开(公告)日：2017-09-12

申请号：US13987667

申请日：2013-08-20

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/53257 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US09411237B2

公开(公告)日：2016-08-09

申请号：US14205324

申请日：2014-03-11

Applicant: Applied Materials, Inc.

Inventor： Peng Xie ,  Christopher Dennis Bencher ,  Huixiong Dai ,  Timothy Michaelson ,  Subhash Deshmukh

IPC: G03F7/40 ,  G03F7/36

CPC classification number: H01L21/67069 ,  C23C16/45544 ,  G03F7/36 ,  G03F7/405 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/68707

Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

Abstract translation: 在一些实施例中，提供了在衬底上形成蚀刻掩模的方法，其包括（1）在衬底上形成抗蚀剂层; （2）将抗蚀剂层的一个或多个区域暴露于能量源，以便改变暴露区域的物理性质和化学性质中的至少一个; （3）对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性，硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积（ALD）室; 和（4）干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

公开(公告)号：US20150162214A1

公开(公告)日：2015-06-11

申请号：US14560525

申请日：2014-12-04

Applicant: Applied Materials, Inc.

Inventor： David Thompson ,  Huixiong Dai ,  Patrick M. Martin ,  Timothy Michaelson ,  Kadthala R. Narendrnath ,  Robert Jan Visser ,  Jingjing Xu ,  Lin Zhang

IPC: H01L21/3213 ,  H01L21/3205

CPC classification number: H01L21/32051 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45551 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76849

Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.

Abstract translation: 提供了选择性沉积的方法。 某些方法描述了提供第一衬底表面; 提供第二衬底表面; 在所述第一和第二衬底表面上沉积第一层膜，其中所述沉积在所述第二衬底表面上具有孵育延迟，使得所述第一衬底表面上的所述第一层膜比沉积在所述第二衬底表面上的所述第一层膜厚 基材表面; 并且在所述第一和第二衬底表面上蚀刻所述第一层膜，其中所述第二衬底表面上的所述第一层膜至少被基本上去除，但所述第一衬底上的所述第一层膜仅被部分地去除。

公开(公告)号：US12198985B2

公开(公告)日：2025-01-14

申请号：US17875527

申请日：2022-07-28

Applicant: Applied Materials, Inc.

Inventor： Wenhui Wang ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/66

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

公开(公告)号：US12085858B2

公开(公告)日：2024-09-10

申请号：US16825388

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Srinivas D. Nemani ,  Steven Hiloong Welch ,  Mangesh Ashok Bangar ,  Ellie Y. Yieh

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/027 ,  H01L21/266 ,  H01L21/311

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/31133

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

公开(公告)号：US11914299B2

公开(公告)日：2024-02-27

申请号：US17898216

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Christopher S. Ngai ,  Ellie Y. Yieh

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/30 ,  G03F7/38 ,  G03F7/16

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/30 ,  G03F7/38 ,  H01L21/0274

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

公开(公告)号：US20210294216A1

公开(公告)日：2021-09-23

申请号：US16825393

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Christopher S. Ngai ,  Ellie Y. Yieh

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/16 ,  G03F7/38 ,  G03F7/30

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

公开(公告)号：US20200075409A1

公开(公告)日：2020-03-05

申请号：US16558711

申请日：2019-09-03

Applicant: Applied Materials, Inc.

Inventor： Wenhui Wang ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.

公开(公告)号：US20190212656A1

公开(公告)日：2019-07-11

申请号：US16244381

申请日：2019-01-10

Applicant: Applied Materials, Inc. ,  International Business Machines Corporation

Inventor： Huixiong Dai ,  Weimin Zeng ,  Daniel Lee Diehl ,  Yong Cao ,  Hsiang Ning Wu ,  Khoi Phan ,  Christopher S. Ngai ,  Mingwei Zhu ,  Michael Stolfi ,  Nelson M. Felix ,  Ekmini Anuja DeSilva ,  Xianmin Tang

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/70058 ,  G03F7/0035 ,  G03F7/2022 ,  G03F7/70033

Abstract: Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.

公开(公告)号：US20180135183A1

公开(公告)日：2018-05-17

申请号：US15806500

申请日：2017-11-08

Applicant: Applied Materials, Inc.

Inventor： Weimin Zeng ,  Yong Cao ,  Daniel Lee Diehl ,  Khoi Phan ,  Huixiong Dai ,  Christopher S. Ngai

IPC: C23C16/56 ,  C23C16/455 ,  G03F1/22

CPC classification number: C23C16/56 ,  C23C14/06 ,  C23C14/5826 ,  C23C14/5846 ,  C23C16/0272 ,  C23C16/455 ,  G03F1/22

Abstract: Processing methods comprising depositing an initial hardmask film on a substrate by physical vapor deposition and exposing the initial hardmask film to a treatment plasma comprising a silane compound to form the hardmask.