公开(公告)号：US08296879B2

公开(公告)日：2012-10-30

申请号：US12945938

申请日：2010-11-15

Applicant: Eric Lin

Inventor： Eric Lin

IPC: A47C19/04 ,  A47C17/64 ,  A47C17/76

CPC classification number: A47C17/72 ,  A47C19/126

Abstract: A foldable bed includes a plurality of connecting bars, a plurality of support bars, and a plurality of stand units. Each of the stand units includes two pivotally connected support legs each having a first end provided with an upper support portion, a second end provided with a lower support portion, and a middle section provided with a pivot portion. Each of the stand units further includes two clamping brackets each mounted on the respective support leg, and two vibration absorbers each mounted in the respective clamping bracket. Thus, when the two support legs are expanded, each of the vibration absorbers on one of the support legs abuts the pivot portion of the other one of the support legs so that the support legs are combined solidly and stably so as to enhance the structural strength of each of the stand units.

Abstract translation: 折叠床包括多个连接杆，多个支撑杆和多个支架单元。 每个支架单元包括两个枢转连接的支撑腿，每个支撑腿具有设置有上支撑部的第一端，设置有下支撑部的第二端和设置有枢转部的中间部。 每个支架单元还包括两个夹持支架，每个夹持支架各自安装在相应的支撑腿上，并且两个振动吸收器各自安装在相应的夹持支架中。 因此，当两个支撑腿膨胀时，其中一个支撑腿上的每个振动吸收器邻接另一个支撑腿的枢转部分，使得支撑腿被牢固且稳定地组合，以便提高结构强度 的每个支架单元。

公开(公告)号：US20100050165A1

公开(公告)日：2010-02-25

申请号：US12613295

申请日：2009-11-05

Applicant: Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

Inventor： Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

IPC: G06F9/44

CPC classification number: G06F9/45516

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

Abstract translation: 公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。 所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。 所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

公开(公告)号：US07634768B2

公开(公告)日：2009-12-15

申请号：US11059902

申请日：2005-02-17

Applicant: Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

Inventor： Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

IPC: G06F9/44

CPC classification number: G06F9/45516

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

Abstract translation: 公开了支持与本地库或应用相关联的被管理应用的执行的方法和装置。 所公开的方法和装置支持与执行平台相同的ISA相关联的虚拟机，而本地库或应用的ISA是不同的ISA。 所公开的方法和装置还支持与分别与若干不同的ISA相关联的几个本地库或应用链接的被管理应用的执行。

公开(公告)号：US20090031044A1

公开(公告)日：2009-01-29

申请号：US12107567

申请日：2008-04-22

Applicant: Craig Barrack ,  James Ching-Shau Yik ,  Rong-Feng Chang ,  Eric Lin

Inventor： Craig Barrack ,  James Ching-Shau Yik ,  Rong-Feng Chang ,  Eric Lin

IPC: G06F15/16 ,  G06F15/173

CPC classification number: H04L49/351 ,  H04L45/745 ,  H04L49/3009

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Abstract translation: 公开了一种用于在计算机网络系统中存储和搜索计算机节点地址的装置和方法。 在一个实施例中，该装置包括诸如开关的帧转发装置。 交换机包括两个MAC地址表，包括主MAC地址表和辅MAC地址表，用于存储和搜索MAC地址。 主表存储包含MAC地址压缩值的记录。 记录包含在使用MAC地址的压缩值作为搜索索引引用的存储位置。 为了解决可能由不同MAC地址压缩到相同值的搜索冲突，主地址表中的每个记录链接到辅助表中的记录链。 辅助表中的记录存储MAC地址的全部值。 辅助地址表中的每个记录链包含本发明的MAC地址。

公开(公告)号：US20080307241A1

公开(公告)日：2008-12-11

申请号：US11808279

申请日：2007-06-08

Applicant: Eric Lin ,  Wen-Chi Hsu

Inventor： Eric Lin ,  Wen-Chi Hsu

IPC: G06F1/28 ,  G06F1/26

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128

Abstract: A microcontroller circuit provides proper clocks to a central processing unit of a microcontroller and peripherals according to a power saving mode and operating conditions of the peripherals. The microcontroller circuit comprises a prescaler, a second multiplexer, a central processing unit, a first switch, a second switch, a first peripheral, and an execution unit. The execution unit is installed in the central processing unit and used for controlling the first switch and the second switch. The switches control the transmission of clocks according to the power saving mode operated by the microcontroller circuit, so that the central processing unit and each peripheral can work with a proper clock to reduce power use.

Abstract translation: 微控制器电路根据节电模式和外围设备的工作条件向微控制器和外设的中央处理单元提供适当的时钟。 微控制器电路包括预分频器，第二多路复用器，中央处理单元，第一开关，第二开关，第一外围设备和执行单元。 执行单元安装在中央处理单元中，用于控制第一开关和第二开关。 这些开关根据微控制器电路所操作的省电模式来控制时钟的传输，使得中央处理单元和每个外围设备可以使用适当的时钟来减少功率使用。

公开(公告)号：US20070232053A1

公开(公告)日：2007-10-04

申请号：US11761360

申请日：2007-06-11

Applicant: Jin-Yuan Lee ,  Eric Lin

Inventor： Jin-Yuan Lee ,  Eric Lin

IPC: H01L23/485

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract translation: 实现了形成集成电路器件的新方法。 该方法包括提供基底。 覆盖衬底上形成牺牲层。 将牺牲层图案化以形成临时的垂直间隔件，其中计划导电接合位置。 沉积在临时垂直间隔物和基底上的导电层。 将导电层图案化以形成覆盖临时垂直间隔物的导电接合位置。 蚀刻掉临时的垂直间隔物以在导电接合位置下方产生空隙。

公开(公告)号：US07260066B2

公开(公告)日：2007-08-21

申请号：US10326352

申请日：2002-12-20

Applicant: Linghsiao Wang ,  Rong-Feng Chang ,  Eric Lin ,  James Ching-Shau Yik

Inventor： Linghsiao Wang ,  Rong-Feng Chang ,  Eric Lin ,  James Ching-Shau Yik

IPC: G01R31/08

CPC classification number: H04L41/0663 ,  H04L41/0677 ,  H04L43/0811 ,  H04L43/10 ,  H04L43/103 ,  H04L49/1523 ,  H04L49/351 ,  H04L49/552 ,  H04L69/40

Abstract: A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

Abstract translation: 一种在高可用性背板架构上主动检测链路故障的方法。 背板系统包括与冗余交换矩阵板操作地通信的冗余节点板。 节点板的上行端口在与交换矩阵板的通信链路的一端在逻辑上分组成中继端口。 发送探测分组，每当接收到指定数量的不良分组，或者空闲定时器到期时，都会设置探测定时器。 如果在探测定时器到期之前接收到对探测分组的响应，则该链路被认为有效，否则链路被认为是失败的。 优选地，节点板或交换矩阵板被配置为适当地处理优选具有相同的源和目的地址的探针包。

公开(公告)号：US20060184920A1

公开(公告)日：2006-08-17

申请号：US11060333

申请日：2005-02-17

Applicant: Yun Wang ,  Miaobo Chen ,  Eric Lin ,  Chris Elford ,  Suresh Srinivas

Inventor： Yun Wang ,  Miaobo Chen ,  Eric Lin ,  Chris Elford ,  Suresh Srinivas

IPC: G06F9/44

CPC classification number: G06F9/45516 ,  G06F9/445

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

公开(公告)号：US20060184919A1

公开(公告)日：2006-08-17

申请号：US11059902

申请日：2005-02-17

Applicant: Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

Inventor： Miaobo Chen ,  Qi Zhang ,  Eric Lin ,  Jianhui Li ,  Yun Wang

IPC: G06F9/44

CPC classification number: G06F9/45516

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

公开(公告)号：US06806570B1

公开(公告)日：2004-10-19

申请号：US10279267

申请日：2002-10-24

Applicant: Jin-Yuan Lee ,  Eric Lin

Inventor： Jin-Yuan Lee ,  Eric Lin

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01028

Abstract: A thermally compliant multi-layer wiring structure on a semiconductor chip is described. The multi-layer wiring structure incorporates an “empty” or air gap under the interconnect wiring and does not allow any thermally induced strains to be transmitted to the interconnecting solder balls. This design is to be used in chip scale packaging applications where printed circuit technology is used as the next level of package.

Abstract translation: 描述了半导体芯片上的热适应性多层布线结构。 多层布线结构在互连布线下方包含“空”或气隙，并且不允许任何热诱导应变传递到互连焊球。 该设计用于将印刷电路技术用作下一级封装的芯片级封装应用。