-
21.发明申请SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI 审中-公开具有高K /金属栅的半导体器件和集成电路，与高K直接接触STI公开(公告)号：US20130146975A1
公开(公告)日：2013-06-13
申请号：US13316677
申请日：2011-12-12
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L29/7833
摘要： A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.
摘要翻译： 具有高k /金属栅极的方法，半导体器件和集成电路，无需与STI直接接触。 将高k电介质和焊盘膜直接沉积到半导体衬底上。 执行浅沟槽隔离，其中浅沟槽直接蚀刻到衬垫膜，高k材料和衬底中。 浅沟槽衬有氧扩散阻挡层，随后填充有绝缘介电材料。 此后，衬垫膜和绝缘电介质凹陷到氧扩散阻挡层仍然保留在绝缘电介质和高k材料之间的点，防止其间的任何接触。 之后形成覆盖该器件的导电栅极。
-
公开(公告)号：US08455932B2
公开(公告)日：2013-06-04
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。
-
公开(公告)号：US20130082311A1
公开(公告)日：2013-04-04
申请号：US13609747
申请日：2012-09-11
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
-
公开(公告)号：US08404540B2
公开(公告)日：2013-03-26
申请号：US13446602
申请日：2012-04-13
IPC分类号： H01L21/8238
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译： 用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。 掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。 在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。
-
公开(公告)号：US20130062704A1
公开(公告)日：2013-03-14
申请号：US13472680
申请日：2012-05-16
IPC分类号： H01L27/092
CPC分类号： H01L29/51 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L29/49 , H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7833
摘要： A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
摘要翻译： 具有多个阈值电压器件的互补金属氧化物半导体（CMOS）结构包括形成在半导体衬底上的第一晶体管器件和第二晶体管器件。 为第一晶体管器件选择性地形成的一组垂直氧化物间隔物与第一晶体管器件的栅介质层直接接触，使得第一晶体管器件相对于第二晶体管器件具有偏移的阈值电压。
-
26.发明授权Thin channel device and fabrication method with a reverse embedded stressor 有权具有反向嵌入式应力源的薄通道器件和制造方法公开(公告)号：US08383474B2
公开(公告)日：2013-02-26
申请号：US12789699
申请日：2010-05-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/7849 , H01L21/26506 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.
摘要翻译： 用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。 可移除的掩埋层设置在第二半导体层上或第二半导体层中。 在第一半导体层上形成具有侧面间隔物的栅极结构。 在源区和漏区的区域中形成凹陷到可移除的掩埋层。 蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。 在底切中形成应力层，形成源区和漏区。
-
公开(公告)号：US08278175B2
公开(公告)日：2012-10-02
申请号：US12813311
申请日：2010-06-10
IPC分类号： H01L21/335
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： 公开了用于制造FET器件结构的方法。 所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。 氧化物元件在制造Fin-FET器件的鳍片上施加压力。 施加的压力在Fin-FET器件的器件沟道中引起压应力。 所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。 所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。 还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有各自具有鳍片的Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
-
28.发明申请FinFET device having reduce capacitance, access resistance, and contact resistance 有权FinFET器件具有降低电容，访问电阻和接触电阻公开(公告)号：US20120193713A1
公开(公告)日：2012-08-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译： 形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。 提供掩埋氧化物，鳍状物，栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。 延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。
-
公开(公告)号：US08207038B2
公开(公告)日：2012-06-26
申请号：US12786397
申请日：2010-05-24
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括具有由第一材料构成的翅片的Fin-FET器件，然后通过外延沉积第二材料而合并在一起。 翅片是使用选择性蚀刻的垂直凹部。 在第一材料和第二材料的增加的表面积上形成连续的硅化物层，导致较小的电阻。 覆盖FET器件的应力衬垫之后被沉积。 还公开了一种FET器件，该FET器件包括多个Fin-FET器件，其翅片由第一材料构成。 FET器件包括第二材料，其外延地融合鳍片。 翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。
-
30.发明申请公开(公告)号：US20110291189A1
公开(公告)日：2011-12-01
申请号：US12789699
申请日：2010-05-28
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/26506 , H01L29/66772 , H01L29/785 , H01L29/78654
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer. A removable buried layer is provided on or in the second semiconductor layer. A gate structure with side spacers is formed on the first semiconductor layer. Recesses are formed down to the removable buried layer in areas for source and drain regions. The removable buried layer is etched away to form an undercut below the dielectric layer below the gate structure. A stressor layer is formed in the undercut, and source and drain regions are formed.
摘要翻译： 用于在半导体层中诱发应力的装置和方法包括提供在第一半导体层和第二半导体层之间形成介电层的基板。 可移除的掩埋层设置在第二半导体层上或第二半导体层中。 在第一半导体层上形成具有侧面间隔物的栅极结构。 在源区和漏区的区域中形成凹陷到可移除的掩埋层。 蚀刻掉可移除的掩埋层，以在栅极结构下面的介电层下方形成底切。 在底切中形成应力层，形成源区和漏区。
-
-
-
-
-
-
-
-
-
搜索结果
277 条记录 (耗时 0.03 秒)
