公开(公告)号：US08802578B2

公开(公告)日：2014-08-12

申请号：US13695191

申请日：2012-07-26

Applicant: Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

Inventor： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

IPC: H01L21/203 ,  H01L21/02 ,  C23C14/34 ,  C23C14/54 ,  C23C14/06 ,  C23C14/18

CPC classification number: H01L21/02186 ,  C23C14/0641 ,  C23C14/18 ,  C23C14/34 ,  C23C14/54 ,  H01L21/2855

Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.

Abstract translation: 公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在惰性气体的离子在电场中加速之后，用钛离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入到晶片的表面中，使得应力被引入到氮化钛层中，其中非晶化部分 通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。 在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在 氮化钛层增加。

公开(公告)号：US08796744B1

公开(公告)日：2014-08-05

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。

公开(公告)号：US20130285127A1

公开(公告)日：2013-10-31

申请号：US13641857

申请日：2012-04-26

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/2255 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present application discloses a method for manufacturing a semiconductor structure, comprises the following steps: providing a substrate and forming a gate stack on the substrate; forming an offset spacer surround the gate stack and a dummy spacer surround the offset spacer; forming the S/D region on both sides of the dummy spacer; removing the dummy spacer and portions of the offset spacer on the surface of the substrate; forming a doped spacer on the sidewall of the offset spacer; forming the S/D extension region by allowing the dopants in doped spacer into the substrate; removing the doped spacer. Accordingly, the present application also discloses a semiconductor structure. In the present disclosure the S/D extension region with high doping concentration and shallow junction depth is formed by the formation of a heavily doped doped spacer, which can be removed in the subsequent procedures, in order to efficiently improve the performance of the semiconductor structure.

Abstract translation: 本申请公开了一种用于制造半导体结构的方法，包括以下步骤：提供衬底并在衬底上形成栅叠层; 形成围绕所述栅极堆叠的偏移间隔物和围绕所述偏移间隔物的虚拟间隔物; 在虚拟间隔物的两侧形成S / D区域; 去除衬垫表面上的虚拟间隔物和偏移间隔物的部分; 在所述偏移间隔物的侧壁上形成掺杂的间隔物; 通过使掺杂间隔物中的掺杂剂进入衬底来形成S / D延伸区域; 去除掺杂间隔物。 因此，本申请还公开了一种半导体结构。 在本公开中，通过形成重掺杂的掺杂间隔物形成具有高掺杂浓度和浅结深度的S / D延伸区，其可以在随后的步骤中去除，以便有效地提高半导体结构的性能 。

公开(公告)号：US08466028B2

公开(公告)日：2013-06-18

申请号：US13322473

申请日：2011-07-27

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L29/66795

Abstract: A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.

Abstract translation: 提供了一种制造多栅装置的方法，包括：提供半导体衬底; 蚀刻半导体衬底以形成突出的鳍; 在鳍片的底部蚀刻半导体衬底，以在翅片和半导体衬底之间形成间隙; 形成覆盖所述半导体基板和所述翅片并填充所述间隙的电介质层; 并蚀刻该电介质层以暴露该翅片的顶部和一部分侧壁。 本发明可以通过简单的工艺实现翅片之间的隔离，成本相对较低，适合大规模的工业应用。

公开(公告)号：US20130105907A1

公开(公告)日：2013-05-02

申请号：US13513198

申请日：2011-11-28

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848

Abstract: The present invention relates to a MOS device and method of manufacturing the same. The device comprises a semiconductor substrate; a channel formed in the semiconductor substrate; a gate stack formed on the channel and a spacer surrounding the gate stack; and source and drain regions formed in the substrates on both sides of the spacer; wherein the gate stack is comprised of an insulating layer and a multi-layer metal gate formed thereon, the multi-layer metal gate is comprised of a strained metal layer for introducing a stress to the channel and a work function regulating layer for regulating the work function of the metal gate, and the work function regulating layer surrounds the strained metal layer from the bottom and sides. The multi-layer metal gate structure overcomes the defect incurred by the fact that a conventional strained metal gate material can not achieve both regulation of work function and effect of application of strain be optimized at the same time.

Abstract translation: 本发明涉及一种MOS器件及其制造方法。 该器件包括半导体衬底; 形成在半导体衬底中的沟道; 形成在沟道上的栅极堆叠和围绕栅极堆叠的间隔物; 以及形成在间隔物的两侧的基板中的源极和漏极区域; 其特征在于，所述栅极叠层由形成在其上的绝缘层和多层金属栅极构成，所述多层金属栅极由用于向所述沟道施加应力的应变金属层和用于调节工件的功函数调节层 金属栅极的功能，功函数调节层从底部和侧面围绕应变金属层。 多层金属栅极结构克服了传统的应变金属栅极材料不能同时实现功能调节和应变效应的事实所引起的缺陷。

公开(公告)号：US20130082362A1

公开(公告)日：2013-04-04

申请号：US13510439

申请日：2011-11-25

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/02 ,  H01L21/31

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/268 ,  H01L21/3105 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.

Abstract translation: 一种半导体器件及其制造方法，其中NMOS器件由通过PECVD具有高紫外光吸收系数的氮化硅膜覆盖，所述氮化硅膜在被受激光激光表面退火时可以很好地吸收紫外光，因此 为了达到良好的脱氢效果，脱氢后，氮化硅膜具有较高的拉伸应力; 由于氮化硅膜具有高的紫外光吸收系数，因此不需要加热基板，从而避免了由于将基板加热脱氢而导致的对器件的不利影响，并且保持了由PECVD工艺引起的热量预算。

公开(公告)号：US20120164838A1

公开(公告)日：2012-06-28

申请号：US13147044

申请日：2011-02-17

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC: H01L21/263

CPC classification number: H01L21/76819 ,  H01L21/31055 ,  H01L21/31116

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.

Abstract translation: 本申请公开提供了一种用于平坦化层间电介质层的方法，包括以下步骤：提供包括至少一个牺牲层和在半导体衬底和第一栅极叠层下的牺牲层下方的至少一个绝缘层的多层结构，执行 多层结构中的第一RIE，其中反应室压力被控制为使得晶片中心处的至少一个牺牲层的部分的蚀刻速率高于晶片的边缘处的蚀刻速率 ，以获得凹蚀刻轮廓; 在所述多层结构上执行第二RIE以完全去除所述牺牲层和所述绝缘层的一部分，从而获得具有用作层间介质层的平坦表面的所述绝缘层。 平坦化处理可以代替用于提供具有平坦表面的层间介电层的CMP工艺，其实现了晶片的相对较大的可用面积。

公开(公告)号：US20120164808A1

公开(公告)日：2012-06-28

申请号：US13129419

申请日：2011-02-17

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US08058907B2

公开(公告)日：2011-11-15

申请号：US12926475

申请日：2010-11-19

Applicant: Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

Inventor： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

IPC: H03K19/20 ,  H03K19/094

CPC classification number: H03K19/01714

Abstract: An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.

公开(公告)号：US07859054B2

公开(公告)日：2010-12-28

申请号：US11561572

申请日：2006-11-20

Applicant: Huaxiang Yin ,  Takashi Noguchi ,  Hyuk Lim ,  Wenxu Xianyu ,  Hans S. Cho

Inventor： Huaxiang Yin ,  Takashi Noguchi ,  Hyuk Lim ,  Wenxu Xianyu ,  Hans S. Cho

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L27/12 ,  H01L29/78609 ,  H01L29/78696

Abstract: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.

Abstract translation: 薄膜晶体管包括具有非线性电子移动路径的Si基通道，设置在沟道两侧的源极和漏极，设置在沟道上方的栅极，介于通道和栅极之间的绝缘体，以及 支撑通道的基板，分别设置在通道的两侧的源极和漏极。