公开(公告)号：US09159734B2

公开(公告)日：2015-10-13

申请号：US13976087

申请日：2011-10-18

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L27/112 ,  H01L23/525 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

摘要翻译： 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。

公开(公告)号：US20140291766A1

公开(公告)日：2014-10-02

申请号：US13995755

申请日：2013-03-30

申请人： Walid M. Hafez ,  Peter J. Vandervoorn ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Peter J. Vandervoorn ,  Chia-Hong Jan

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/1608 ,  H01L29/161

摘要： Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

摘要翻译： 公开了在finFET制造工艺流程期间在基于鳍片的场效应晶体管（finFET）架构上形成平面状晶体管器件的技术。 在一些实施例中，平面状晶体管可以包括例如半导体层，该半导体层被生长以局部地合并/桥接finFET架构的多个相邻鳍片，并且随后被平坦化以提供高质量的平面表面，平面 形晶体管。 在一些情况下，半导体合并层可以是桥接外延生长，例如包括外延硅。 在一些实施例中，这样的平面状器件可以辅助例如模拟，高电压，宽Z晶体管制造。 此外，在finFET流动期间提供这样的平面状器件可以允许形成晶体管器件，例如，显示出更低的电容，更宽的Z和/或更少的高电场位置，以改善高电压可靠性，其可以 在某些情况下，使这种设备有利于模拟设计。

公开(公告)号：US20140291737A1

公开(公告)日：2014-10-02

申请号：US13995717

申请日：2013-03-29

申请人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

发明人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78

摘要： Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.

摘要翻译： 公开了用于形成具有延伸的凹入间隔物和源极/漏极（S / D）区域的晶体管架构的技术。 在一些实施例中，可以例如在鳍式场效应晶体管（finFET）的鳍的顶部形成凹部，使得凹部允许在鳍状物FET中形成延伸的凹入的间隔物和S / D区域 它们与栅极堆叠相邻。 在一些情况下，该配置在鳍的顶部提供更高的电阻路径，这可以减少finFET中的栅极引起的漏极泄漏（GIDL）。 在一些实施例中，可以提供GIDL的开始的精确调整。 一些实施例可以提供结漏电（Lb）的降低和阈值电压（VT）的同时增加。 所公开的技术可以用平面和非平面鳍状结构来实现，并且在一些实施例中可以用于标准金属氧化物半导体（MOS）和互补MOS（CMOS）工艺流程中。

公开(公告)号：US08426927B2

公开(公告)日：2013-04-23

申请号：US13107783

申请日：2011-05-13

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20120163103A1

公开(公告)日：2012-06-28

申请号：US12976630

申请日：2010-12-22

申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US20100163952A1

公开(公告)日：2010-07-01

申请号：US12347904

申请日：2008-12-31

申请人： Chia-Hong Jan ,  Walid M. Hafez

发明人： Chia-Hong Jan ,  Walid M. Hafez

IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L21/04 ,  H01L29/41

CPC分类号： H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.

摘要翻译： 描述了具有集成的高k电介质层和金属控制栅极的半导体器件。 对其制造方法进行说明。 半导体器件的实施例包括设置在浮置栅极上的高k电介质层。 高k电介质层限定凹陷。 金属控制门形成在凹槽中。

公开(公告)号：US08889508B2

公开(公告)日：2014-11-18

申请号：US14313678

申请日：2014-06-24

申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

摘要翻译： 描述了用于非平面半导体器件结构的精密电阻器。 在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。 晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。 在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。 电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。 第一和第二晶体管结构分别由第一和第二半导体鳍形成。

公开(公告)号：US08741720B2

公开(公告)日：2014-06-03

申请号：US13857578

申请日：2013-04-05

申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC分类号： H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US08669617B2

公开(公告)日：2014-03-11

申请号：US12978182

申请日：2010-12-23

申请人： Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Walid M. Hafez

发明人： Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Walid M. Hafez

IPC分类号： H01L27/088

CPC分类号： H01L21/823857 ,  H01L21/26506 ,  H01L21/28158 ,  H01L21/2822 ,  H01L21/823462 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided.

摘要翻译： 提供了具有至少三种和至少四种不同类型的晶体管的器件，其中晶体管至少区别于栅极电介质区域的厚度和/或组成。 还提供了制造具有三个至少四种不同类型晶体管的器件的方法，其至少区别于栅极电介质区域的厚度和/或组成。

公开(公告)号：US20140001569A1

公开(公告)日：2014-01-02

申请号：US13536732

申请日：2012-06-28

申请人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.

摘要翻译： 描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。 例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。 第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。 第一栅极结构包括由设置在第一鳍片有源区上的第一介电层和设置在第一介电层上的第二不同介电层构成的第一栅极电介质。 半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。 第二栅极结构包括由设置在第二鳍片有源区上的第二介电层构成的第二栅极电介质。