公开(公告)号：US06811955B2

公开(公告)日：2004-11-02

申请号：US10235185

申请日：2002-09-04

Applicant: Wei-Jen Wu ,  Sung-Cheng Chiu ,  Ching-Jiunn Huang ,  Cheng-Ming Wu

Inventor： Wei-Jen Wu ,  Sung-Cheng Chiu ,  Ching-Jiunn Huang ,  Cheng-Ming Wu

IPC: G03F726

CPC classification number: G03F7/3021

Abstract: A method for developing a photo-exposed photoresist layer to improve a critical dimension uniformity (CDU) for a semiconductor device manufacturing process including providing a semiconductor process wafer having a process surface comprising a photoresist layer photo-exposed according to an exposure pattern; dispensing a predetermined amount of developer solution over a stationary semiconductor process wafer to form a film of developer solution covering the process surface; partially developing the exposed portions of the photoresist layer comprising maintaining the semiconductor process wafer in a stationary position for a predetermined time period; rotating the semiconductor process wafer for a predetermined period of time to remove a portion of the developer solution; and, repeating the steps of dispensing, partially developing, and rotating, for a predetermined number of repetition cycles to complete a photoresist development process.

公开(公告)号：US06743735B2

公开(公告)日：2004-06-01

申请号：US10102288

申请日：2002-03-19

Applicant: Po-Tao Chu ,  Hsin-Yuan Chen ,  Chung-Jen Chen ,  Tai-Ming Yang ,  Cheng-Ming Wu

Inventor： Po-Tao Chu ,  Hsin-Yuan Chen ,  Chung-Jen Chen ,  Tai-Ming Yang ,  Cheng-Ming Wu

IPC: H01L21302

CPC classification number: G03F7/2026 ,  G03F7/2028 ,  H01L23/544 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/906 ,  H01L2924/00

Abstract: Removing photoresist from alignment marks on a semiconductor wafer using a wafer edge exposure process is disclosed. The alignment marks on the wafer are covered by photoresist used in conjunction with semiconductor processing of one or more layers deposited on the semiconductor wafer. One or more parts of the edge of the wafer are exposed to remove the photoresist from these parts and thus reveal alignment marks on the wafer. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.

Abstract translation: 公开了使用晶片边缘曝光工艺从半导体晶片上的对准标记去除光致抗蚀剂。 晶片上的对准标记由与沉积在半导体晶片上的一个或多个层的半导体处理结合使用的光致抗蚀剂覆盖。 暴露晶片边缘的一个或多个部分以从这些部分去除光致抗蚀剂，从而在晶片上露出对准标记。 晶片的一个或多个部分的曝光是在不执行光刻清除工艺的情况下实现的。 相反，本发明利用晶片边缘曝光（WEE）工艺。 一旦执行了WEE过程，可以使用所显示的对准标记对准它们来沉积后续层。

公开(公告)号：US06187659B1

公开(公告)日：2001-02-13

申请号：US09368861

申请日：1999-08-06

Applicant: Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L214763

CPC classification number: H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897

Abstract: A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.

Abstract translation: 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。

公开(公告)号：US06168984A

公开(公告)日：2001-01-02

申请号：US09419103

申请日：1999-10-15

Applicant: Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

Inventor： Chue-San Yoo ,  Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Tse-Liang Ying

IPC: H01L218242

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

Abstract: A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.

Abstract translation: 已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。 减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。 在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。 然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。 在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

公开(公告)号：US6165839A

公开(公告)日：2000-12-26

申请号：US92880

申请日：1998-06-08

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10811 ,  H01L28/91

Abstract: A process for forming a DRAM, cylindrical shaped, stacked capacitor structure, located under a bit line structure, has been developed. The process features defining a polysilicon cell plate structure, during the same photolithotgraphic and anisotropic etching procedures, used to open a bit line contact hole. The bit line contact hole is formed by first opening a top portion of the bit line contact hole, using a photoresist shape as an etch mask, and after the formation of silicon nitride spacers, on the sides of the top portion of the bit line contact hole, the bottom portion of the bit line contact hole is opened, using silicon nitride as an etch mask.

Abstract translation: 已经开发了一种用于形成位于位线结构下方的DRAM，圆柱形，堆叠式电容器结构的工艺。 在用于打开位线接触孔的相同的光电影和各向异性蚀刻过程中，限定多晶硅单元板结构的过程特征。 位线接触孔通过使用光致抗蚀剂形状作为蚀刻掩模首先打开位线接触孔的顶部，并且在形成氮化硅间隔物之后，在位线接触的顶部的侧面 使用氮化硅作为蚀刻掩模，打开位线接触孔的底部。

公开(公告)号：US6136695A

公开(公告)日：2000-10-24

申请号：US366741

申请日：1999-08-04

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Ming-Hsiung Chiang

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Ming-Hsiung Chiang

IPC: H01L21/314 ,  H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L21/3144

Abstract: A method for forming a self aligned contact wherein a dielectric layer is formed directly on a conductive structure according the present invention. A semiconductor structure having a polysilicon conductive structure (such as a bit line) thereon is provided. A contact area is located on the semiconductor structure adjacent to the conductive structure. A dielectric layer, preferably composed of silicon oxide is formed over the conductive structure and the semiconductor structure. A top hard mask layer is formed over the dielectric layer. A contact opening is formed in the top hard mask layer and the dielectric layer using an etch selective to oxide over polysilicon, thereby exposing the contact region of the semiconductor structure adjacent to the conductive structure without etching through the conductive structure. A first lining dielectric layer, a second lining dielectric layer, and a third lining dielectric layer are sequentially deposited on the sidewalls of the contact opening and on the contact area of the semiconductor structure. The first and third lining dielectric layers are preferably composed of silicon dioxide and the third lining dielectric layer is preferably composed of silicon nitride. The third lining dielectric layer is anisotropically etched forming a second contact opening in the second lining dielectric layer over the contact area while leaving a spacer on the sidewall of the contact opening. The second lining dielectric layer and the first lining dielectric layer are anisotropically etched to expose the contact area of the semiconductor structure, while the spacer prevents erosion of the second lining dielectric layer and the first lining dielectric layer on the sidewall of the contact opening. The remaining spacer is removed, preferably using a buffered HF dip. A polysilicon contact layer is formed on the second lining dielectric layer and on the contact area of the semiconductor structure.

Abstract translation: 一种形成自对准接触的方法，其中介电层直接形成在根据本发明的导电结构上。 提供具有多晶硅导电结构（例如位线）的半导体结构。 接触区域位于与导电结构相邻的半导体结构上。 在导电结构和半导体结构之上形成优选由氧化硅构成的电介质层。 在电介质层上方形成顶部硬掩模层。 在顶部硬掩模层和电介质层中使用对多晶硅上的氧化物的选择性蚀刻形成接触开口，由此暴露出与导电结构相邻的半导体结构的接触区域而不通过导电结构进行蚀刻。 第一衬里介电层，第二衬里电介质层和第三衬里电介质层依次沉积在接触开口的侧壁和半导体结构的接触区域上。 第一和第三衬里电介质层优选由二氧化硅构成，第三衬里电介质层优选由氮化硅构成。 第三衬里电介质层被各向异性蚀刻，在接触区域上形成第二衬里介电层中的第二接触开口，同时在接触开口的侧壁上留下间隔物。 第二衬里电介质层和第一衬里电介质层被各向异性蚀刻以暴露半导体结构的接触面积，而间隔物防止第二衬里介电层和接触开口侧壁上的第一衬里介电层的侵蚀。 除去剩余的间隔物，优选使用缓冲的HF浸渍。 在第二衬里电介质层和半导体结构的接触区域上形成多晶硅接触层。

公开(公告)号：US6107155A

公开(公告)日：2000-08-22

申请号：US131118

申请日：1998-08-07

Applicant: Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10873

Abstract: A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings, which are generally recessed due to overetching to completely remove the polysilicon on the insulating surface. A Si.sub.3 N.sub.4 etch-stop layer is deposited to protect the exposed sidewalls in the first openings. A disposable second SiO.sub.2 insulating layer is deposited and second openings are etched over and to the node contacts for forming bottom electrodes. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the Si.sub.3 N.sub.4 on the sidewalls protects the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an inter-electrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.

Abstract translation: 描述了一种用于形成用于DRAM的堆叠电容器的修改方法，其规避了由于未对准引起的氧化物侵蚀。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 第一个开口蚀刻电容器节点触点。 沉积多晶硅层并将其回蚀刻以形成第一开口中的节点接触，其通常由于过蚀刻而凹陷以完全去除绝缘表面上的多晶硅。 沉积Si 3 N 4蚀刻停止层以保护第一开口中暴露的侧壁。 沉积一次性第二SiO 2绝缘层，并且在节点触点上蚀刻第二开口并形成底部电极。 沉积保形第二多晶硅层并在第二开口中化学/机械抛光以形成底部电极。 通过湿法蚀刻去除蚀刻停止层来除去第二绝缘层。 当第二开口在节点接触开口上不对准时，侧壁上的Si 3 N 4保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 现在通过在底部电极上形成电极间电介质层，并沉积和构图顶部电极的第三多晶硅层来完成电容器。

公开(公告)号：US6037213A

公开(公告)日：2000-03-14

申请号：US89550

申请日：1998-06-03

Applicant: Cheng-Yeh Shih ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Cheng-Yeh Shih ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node contacts are formed. First openings for node contacts are etched in the polish-back and second insulating layers to the etch-stop layer aligned over the device areas. Wider second openings, aligned over the first openings, are etched through the polish-back layer, and also removes the etch-stop layer in the first openings. The second insulating layer in the second openings is etched to the etch-stop layer, while the first insulating layer is etched in the first openings for node contact openings. A doped first polysilicon layer is deposited and polished back to the polish-back detect layer to form concurrently the node contacts in the first openings and bottom electrodes in the second openings. The second insulating layer is removed by a wet etch. A thin dielectric layer is deposited, and top electrodes are formed from a second polysilicon layer. The etch-stop layer provides better control of the etching depth for the first and second openings that improves reliability while providing a simple manufacturing process.

Abstract translation: 描述了一种用于制造用于DRAM的圆柱形叠层电容器的方法。 在器件区域上形成平面的第一绝缘层。 沉积有蚀刻停止层，第二绝缘层和抛光端点检测层，其中形成具有节点接触的圆柱形电容器。 用于节点接触的第一开口在抛光和第二绝缘层中蚀刻到在器件区域上对准的蚀刻停止层。 在第一开口上对准的更宽的第二开口被蚀刻穿过抛光层，并且还去除第一开口中的蚀刻停止层。 将第二开口中的第二绝缘层蚀刻到蚀刻停止层，同时在用于节点接触开口的第一开口中蚀刻第一绝缘层。 掺杂的第一多晶硅层被沉积并抛光回到抛光检测层，以同时形成第二开口中的第一开口和底部电极中的节点接触。 通过湿蚀刻去除第二绝缘层。 沉积薄介电层，并且顶电极由第二多晶硅层形成。 蚀刻停止层提供对第一和第二开口的蚀刻深度的更好控制，其在提供简单的制造工艺的同时提高了可靠性。

公开(公告)号：US6033981A

公开(公告)日：2000-03-07

申请号：US358988

申请日：1999-07-22

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/31116 ,  H01L21/31612

Abstract: A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and the substrate. The HDP layer is etched through to expose the edges of the conducting lines. An insulating layer is deposited overlying the HDP layer and conducting lines. A chemical mechanical polishing (CMP) is used to remove the peaks of the insulating layer, exposing the HDP layer in the area overlying the conducting lines. The exposed HDP layer is etched away exposing the top surface of the conducting lines. The insulating layer is then selectively etched away. Spacers may then be added along the sidewalls of the conductor. Finally, a second HDP layer is deposited overlying the first dielectric layer and conducting lines free from voids. The integrated circuit device is completed.

Abstract translation: 实现了在紧密间隔的导电线之间消除电介质氧化物中的空隙的方法。 提供基板。 在基板上设置窄间隔的导线。 沉积在导电线和衬底上的高密度等离子体（HDP）电介质层。 HDP层被蚀刻通过以暴露导线的边缘。 绝缘层沉积在HDP层和导线上。 使用化学机械抛光（CMP）去除绝缘层的峰，使覆盖导电线的区域中的HDP层暴露。 暴露的HDP层被蚀刻掉，暴露导电线的顶表面。 然后选择性地蚀刻绝缘层。 然后可以沿着导体的侧壁添加间隔物。 最后，沉积第二HDP层，覆盖第一介电层和没有空隙的导电线。 集成电路装置完成。