SIMD integer multiply-accumulate instruction for multi-precision arithmetic
    25.
    发明授权
    SIMD integer multiply-accumulate instruction for multi-precision arithmetic 有权
    用于多精度算术的SIMD整数乘法累加指令

    公开(公告)号:US09235414B2

    公开(公告)日:2016-01-12

    申请号:US13992728

    申请日:2011-12-19

    IPC分类号: G06F7/52 G06F9/30 G06F9/38

    摘要: A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.

    摘要翻译: 乘法和累加(MAC)指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器,作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。 第一向量寄存器存储第一因子,第二向量寄存器存储部分和。 执行MAC指令以将第一因子与隐含的第二因子相乘以生成乘积,并将部分和添加到乘积以生成结果。 第一个因素,隐含的第二个因子和部分和具有相同的数据宽度,产品的数据宽度是两倍。 结果的最大一半存储在第三向量寄存器中,结果的最低有效半存储在第二向量寄存器中。

    Bit range isolation instructions, methods, and apparatus
    26.
    发明授权
    Bit range isolation instructions, methods, and apparatus 有权
    位范围隔离指令,方法和设备

    公开(公告)号:US09003170B2

    公开(公告)日:2015-04-07

    申请号:US12645307

    申请日:2009-12-22

    摘要: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    摘要翻译: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有:(1)具有第一端的第一范围,其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和(2)与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位,执行指令都可以完成,而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元,具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

    Protected Power Management Mode In A Processor
    28.
    发明申请
    Protected Power Management Mode In A Processor 有权
    处理器中的受保护的电源管理模式

    公开(公告)号:US20150006917A1

    公开(公告)日:2015-01-01

    申请号:US13930044

    申请日:2013-06-28

    IPC分类号: G06F1/26

    摘要: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,处理器包括多个核。 每个核心包括用于检测一个或多个电力管理事件的核心电力单元,并且响应于一个或多个电力管理事件,在核心中发起受保护的电力管理模式。 在受保护的电源管理模式下,可能会禁用到核心的软件中断。 核心是在受保护的电源管理模式下执行电源管理代码。 描述和要求保护其他实施例。

    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM
    30.
    发明申请
    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM 有权
    指令处理程序,方法和系统处理BLAKE安全冲洗算法

    公开(公告)号:US20140016773A1

    公开(公告)日:2014-01-16

    申请号:US13976741

    申请日:2011-12-22

    IPC分类号: H04L9/28

    摘要: A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.

    摘要翻译: 一种方面的方法包括:接收指示具有至少一组四个状态矩阵数据元素的第一源的指令,其表示对密码散列算法的G函数的四个输入的完整集合。 该算法使用十六个数据元素状态矩阵,并在列和对角线之间更新数据元素。 该指令还指示具有表示消息和常数数据的数据元素的第二源。 响应该指令,结果存储在指令指示的目的地中。 结果包括更新的状态矩阵数据元素,包括至少一组四个更新的状态矩阵数据元素。 四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。