公开(公告)号：US20100244288A1

公开(公告)日：2010-09-30

申请号：US12813808

申请日：2010-06-11

申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

IPC分类号： H01L23/544 ,  G03B27/52

CPC分类号： G03F7/70433

摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

公开(公告)号：US20090006840A1

公开(公告)日：2009-01-01

申请号：US10372399

申请日：2003-02-25

申请人： Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

发明人： Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

IPC分类号： G06F15/16 ,  H04L9/32 ,  G06F21/00 ,  H04L9/00

CPC分类号： H04L61/20 ,  H04L29/12207 ,  H04L63/0492 ,  H04L67/125 ,  H04L67/18

摘要： A computer architecture for enterprise device applications provides a real-time, bi-directional communication layer for device communication. An identity-based communications layer provides for secure, end-to-end telemetry and control communications by enabling mutual authentication and encryption between the devices and the enterprise. The identity-based communications layer is situated between a network layer and an application layer and transmits a message between two devices identified by a global address. The global address specifies a protocol, a network, and an address meaningful for the combination of the protocol and the network.

摘要翻译： 用于企业设备应用的计算机体系结构提供用于设备通信的实时双向通信层。 基于身份的通信层通过实现设备和企业之间的相互认证和加密来提供安全的端到端遥测和控制通信。 基于身份的通信层位于网络层和应用层之间，并且在由全局地址识别的两个设备之间传送消息。 全局地址指定协议，网络和对协议和网络的组合有意义的地址。

公开(公告)号：US20070266557A1

公开(公告)日：2007-11-22

申请号：US11437456

申请日：2006-05-19

申请人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

发明人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

IPC分类号： H05K3/30 ,  G06F19/00

CPC分类号： H05K3/303 ,  G02B6/4226 ,  H01L22/12 ,  H01L24/01 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K2201/10083 ,  H05K2201/10151 ,  H05K2201/10674 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49133

摘要： One embodiment of the present invention provides a system that automatically detects and corrects a misalignment of a semiconductor chip. During operation, the system uses a position-detection mechanism integrated with the chip to determine the misalignment of the chip from a desired alignment for the chip. Next, the system uses an actuation mechanism integrated with the chip to automatically correct the misalignment, thereby improving performance and reliability of the chip.

摘要翻译： 本发明的一个实施例提供一种自动检测和校正半导体芯片的未对准的系统。 在操作期间，系统使用与芯片集成的位置检测机构来确定芯片与芯片的期望对准的未对准。 接下来，系统使用与芯片集成的致动机构来自动校正未对准，从而提高芯片的性能和可靠性。

公开(公告)号：US08283766B2

公开(公告)日：2012-10-09

申请号：US12874446

申请日：2010-09-02

申请人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

发明人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/02

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1015 ,  H01L2924/10155 ,  H01L2924/151

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

摘要翻译： 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件被电气和机械耦合到暴露的焊盘。 例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。 此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部段平行于该方向，并机械耦合到斜坡部件。 这些端段可以促进芯片和斜坡部件之间的信号的高带宽通信，例如通过接近通信。

公开(公告)号：US07949436B2

公开(公告)日：2011-05-24

申请号：US11437456

申请日：2006-05-19

申请人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

发明人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

IPC分类号： G05D1/02

CPC分类号： H05K3/303 ,  G02B6/4226 ,  H01L22/12 ,  H01L24/01 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K2201/10083 ,  H05K2201/10151 ,  H05K2201/10674 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49133

摘要： One embodiment of the present invention provides a system that automatically detects and corrects a misalignment of a semiconductor chip. During operation, the system uses a position-detection mechanism integrated with the chip to determine the misalignment of the chip from a desired alignment for the chip. Next, the system uses an actuation mechanism integrated with the chip to automatically correct the misalignment, thereby improving performance and reliability of the chip.

摘要翻译： 本发明的一个实施例提供一种自动检测和校正半导体芯片的未对准的系统。 在操作期间，系统使用与芯片集成的位置检测机构来确定芯片与芯片的期望对准的未对准。 接下来，系统使用与芯片集成的致动机构来自动校正未对准，从而提高芯片的性能和可靠性。

公开(公告)号：US20110018120A1

公开(公告)日：2011-01-27

申请号：US12507349

申请日：2009-07-22

申请人： Robert J. Drost ,  James G. Mitchell ,  David C. Douglas

发明人： Robert J. Drost ,  James G. Mitchell ,  David C. Douglas

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/72 ,  H01L24/90 ,  H01L25/0652 ,  H01L29/0657 ,  H01L2223/6638 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

摘要翻译： 描述了芯片封装。 该芯片封装包括彼此偏移的半导体管芯或芯片堆叠，由此限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件电耦合到暴露的焊盘。 例如，斜坡部件可以使用：微弹簧，各向异性膜和/或焊料电耦合到半导体管芯。 因此，电触点可以具有导电性，电容性或通常的复阻抗。 此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。 通过消除对半导体管芯中昂贵且耗费大量的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。

公开(公告)号：US07763396B2

公开(公告)日：2010-07-27

申请号：US11355757

申请日：2006-02-16

申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

IPC分类号： G03F9/00

CPC分类号： G03F7/70433

摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

公开(公告)号：US20090007217A1

公开(公告)日：2009-01-01

申请号：US11567532

申请日：2006-12-06

申请人： Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

发明人： Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

IPC分类号： G06F21/00

CPC分类号： H04L61/20 ,  H04L29/12207 ,  H04L63/0492 ,  H04L67/125 ,  H04L67/18 ,  H04W12/02

摘要： A computer architecture for enterprise device applications provides a real-time, bi-directional communication layer for device communication. An identity-based communications layer provides for secure, end-to-end telemetry and control communications by enabling mutual authentication and encryption between the devices and the enterprise. A unique identity is assigned to each device, user and application to provide security services. A communications session is established between two devices using an authentication service that authenticates the device that is initiating the establishment of the communications session with another device. After authenticating the initiating device, the authentication service provides to the initiating device the network address of the other device and an authentication credential for use in the communications session between the initiating device and the other device.

摘要翻译： 用于企业设备应用的计算机体系结构提供用于设备通信的实时双向通信层。 基于身份的通信层通过实现设备和企业之间的相互认证和加密来提供安全的端到端遥测和控制通信。 为每个设备，用户和应用程序分配唯一的身份以提供安全服务。 使用认证服务的两个设备之间建立通信会话，认证服务认证正在发起与另一设备建立通信会话的设备。 在认证发起设备之后，认证服务向发起设备提供其他设备的网络地址，以及在启动设备和其他设备之间的通信会话中使用的认证凭证。

公开(公告)号：US20080301298A1

公开(公告)日：2008-12-04

申请号：US10372398

申请日：2003-02-25

申请人： Linda Bernardi ,  Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

发明人： Linda Bernardi ,  Chet Birger ,  David C. Douglas ,  Steven Rosenthal ,  Kenneth R. Traub

IPC分类号： G06F15/173

CPC分类号： H04L61/20 ,  H04L29/12207 ,  H04L63/0492 ,  H04L67/125 ,  H04L67/18 ,  H04W12/02

摘要： A computer architecture for enterprise device applications that provides a real-time, bi-directional communication layer for device communication. An identity-based communications layer provides for secure, end-to-end telemetry and control communications by enabling mutual authentication and encryption between the devices and the enterprise. A unique identity is assigned to each device, user and application to provide security services. The unique identity is independent of a network-address. Security information and a network address may be associated with the unique identity.

摘要翻译： 一种用于企业设备应用程序的计算机体系结构，为设备通信提供实时的双向通信层。 基于身份的通信层通过实现设备和企业之间的相互认证和加密来提供安全的端到端遥测和控制通信。 为每个设备，用户和应用程序分配唯一的身份以提供安全服务。 独特的身份与网络地址无关。 安全信息和网络地址可以与唯一身份相关联。

公开(公告)号：US5148547A

公开(公告)日：1992-09-15

申请号：US704688

申请日：1991-05-17

申请人： Brewster A. Kahle ,  David C. Douglas ,  Alexander Vasilevsky ,  David P. Christman ,  Shaw W. Yang ,  Kenneth W. Crouch

发明人： Brewster A. Kahle ,  David C. Douglas ,  Alexander Vasilevsky ,  David P. Christman ,  Shaw W. Yang ,  Kenneth W. Crouch

IPC分类号： G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17368 ,  G06F15/8007

摘要： A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors. In accordance with a preferred embodiment of the invention, three or more transposers are used in connection with each word-oriented processor so as to provide a pipelining capability that significantly enhances processing speeds.

摘要翻译： 公开了一种并行处理器，其结合了位串行处理器阵列和面向字的处理器阵列的优点。 此外，本发明提供了以比特串行方式组织的数据与并行组织的数据之间的就绪通信。 处理器包括多个面向字的处理器，与每个处理器相关联的至少一个转移器，所述转置器具有n位串行输入和m位并行输出以及与转移器的每个位串行输入相关联的位串行处理器。 并行处理器还包括用于每个位串行处理器的存储器和互连存储器的数据总线，位串行处理器和转移器的位串行输入。 转换器将串行输入转换为并行的字组织输出，这些输出作为输入提供给面向字的处理器。 根据本发明的优选实施例，与每个面向字的处理器结合使用三个或更多个转移器，以提供显着增强处理速度的流水线能力。