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    Method and apparatus for fabricating semiconductor chips using varying areas of precision
    2.
    发明授权
    Method and apparatus for fabricating semiconductor chips using varying areas of precision 有权
    使用不同精度的区域制造半导体芯片的方法和装置

    公开(公告)号：US07763396B2

    公开(公告)日：2010-07-27

    申请号：US11355757

    申请日：2006-02-16

    申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    IPC分类号： G03F9/00

    CPC分类号： G03F7/70433

    摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

    摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

    METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR CHIPS USING VARYING AREAS OF PRECISION
    3.
    发明申请
    METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR CHIPS USING VARYING AREAS OF PRECISION 审中-公开
    使用精度变化区域制作半导体器件的方法和装置

    公开(公告)号：US20100244288A1

    公开(公告)日：2010-09-30

    申请号：US12813808

    申请日：2010-06-11

    申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    IPC分类号： H01L23/544 ,  G03B27/52

    CPC分类号： G03F7/70433

    摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

    摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

    Offset cancellation in a capacitively coupled amplifier
    6.
    发明授权
    Offset cancellation in a capacitively coupled amplifier 有权
    电容耦合放大器中的偏移消除

    公开(公告)号：US08102203B2

    公开(公告)日：2012-01-24

    申请号：US11860693

    申请日：2007-09-25

    申请人： Robert J. Drost ,  Robert Proebsting ,  Arlene Proebsting, legal representative ,  Scott M. Fairbanks ,  Ronald Ho

    发明人： Robert J. Drost ,  Robert Proebsting ,  Scott M. Fairbanks ,  Ronald Ho

    IPC分类号： H03F1/02

    CPC分类号： H03F3/45973 ,  H03F1/30

    摘要： A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

    摘要翻译： 描述了用于校准用于放大电容耦合通信信号的放大器的偏移电压的方法。 在该过程中，将公共电压施加到放大器的一个或多个输入。 接下来，迭代地，测量放大器的输出，并且将电荷施加到一个或多个输入，直到偏移电压小于预定值。 注意，应用电荷可以包括应用一个或多个充电脉冲的序列。

    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION
    7.
    发明申请
    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION 有权
    通过使用电容耦合来降低功耗以实现主要检测的设备

    公开(公告)号：US20120007699A1

    公开(公告)日：2012-01-12

    申请号：US13235152

    申请日：2011-09-16

    申请人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    发明人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    IPC分类号： H03H7/00

    CPC分类号： G06F1/189

    摘要： One embodiment of the present invention provides a system that reduces power consumption by using capacitive coupling to perform a majority detection operation. The system starts by driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. Next, the system feeds signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The system then uses the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by the computer system.

    摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的系统。 系统通过将多个信号驱动到多个从动线上开始。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 接下来，系统将多数检测线上的信号馈送到差分接收器的偏置电压。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 然后，系统使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。

    Using floating fill metal to reduce power use for proximity communication
    8.
    发明授权
    Using floating fill metal to reduce power use for proximity communication 有权
    使用浮动填充金属来减少接近通信的电力

    公开(公告)号：US07994604B2

    公开(公告)日：2011-08-09

    申请号：US12317606

    申请日：2008-12-24

    申请人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Robert Proebsting ,  Arlene Proebsting, legal representative

    发明人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Robert Proebsting

    IPC分类号： H01L23/52 ,  H01L23/538

    CPC分类号： H01L23/48 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit a signal using proximity communication. A layer of fill metal is located in proximity to this array of transmission pads, wherein the layer of fill metal is “floating” (e.g., not connected to any signal). Leaving this layer of fill metal floating reduces the parasitic capacitance for the array of transmission pads, which can reduce the amount of power needed to transmit the signal.

    摘要翻译： 本发明的一个实施例提供一种有助于减少邻近通信所需的功率的系统。 该系统包括具有使用接近通信传输信号的传输焊盘阵列的集成电路。 填充金属层位于该传输焊盘阵列附近，其中填充金属层“浮动”（例如，未连接到任何信号）。 离开这层填充金属浮动可以减少传输焊盘阵列的寄生电容，这可以减少传输信号所需的功率。

    Multi-phase clocking of integrated circuits using photonics
    10.
    发明授权
    Multi-phase clocking of integrated circuits using photonics 有权
    使用光子学的集成电路的多相时钟

    公开(公告)号：US07747173B1

    公开(公告)日：2010-06-29

    申请号：US11728841

    申请日：2007-03-26

    申请人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

    发明人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

    IPC分类号： H04B10/00

    CPC分类号： H04B10/801

    摘要： Embodiments of an integrated circuit are described. This integrated circuit includes a clock-generator circuit configured to provide a clock signal and an optical clock path coupled to the clock-generator circuit. Note that the optical clock path is configured to distribute optical signals corresponding to the clock signal. Furthermore, note that a given optical signal has a phase which is different than phases of the other optical signals.

    摘要翻译： 描述集成电路的实施例。 该集成电路包括时钟发生器电路，其被配置为提供时钟信号和耦合到时钟发生器电路的光时钟通路。 注意，光时钟路径被配置为分配对应于时钟信号的光信号。 此外，注意，给定的光信号具有与其它光信号的相位不同的相位。