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    Structures including means for lateral current carrying capability improvement in semiconductor devices
    22.
    发明授权
    Structures including means for lateral current carrying capability improvement in semiconductor devices 有权
    结构包括用于半导体器件中横向电流承载能力改进的装置

    公开(公告)号：US07904868B2

    公开(公告)日：2011-03-08

    申请号：US11873711

    申请日：2007-10-17

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA
    23.
    发明申请
    IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA 有权
    通过硅片的在线深度测量

    公开(公告)号：US20100210043A1

    公开(公告)日：2010-08-19

    申请号：US12371724

    申请日：2009-02-16

    申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    IPC分类号： H01L21/66 ,  G06F19/00

    CPC分类号： H01L22/34 ,  H01L2924/3011

    摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

    摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

    LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    24.
    发明申请
    LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件中的横向电流承载能力改进

    公开(公告)号：US20080308940A1

    公开(公告)日：2008-12-18

    申请号：US12198196

    申请日：2008-08-26

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/522

    CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    Metal wiring structure for integration with through substrate vias
    26.
    发明授权
    Metal wiring structure for integration with through substrate vias 有权
    金属布线结构，用于与基板通孔集成

    公开(公告)号：US08234606B2

    公开(公告)日：2012-07-31

    申请号：US13080716

    申请日：2011-04-06

    申请人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    发明人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    IPC分类号： G06F17/50 ,  H01L29/40

    CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

    摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。

    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR
    27.
    发明申请
    THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
    热控制的金属电阻器

    公开(公告)号：US20120146186A1

    公开(公告)日：2012-06-14

    申请号：US12962722

    申请日：2010-12-08

    申请人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

    摘要翻译： 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

    Optically transparent wires for secure circuits and methods of making same
    28.
    发明授权
    Optically transparent wires for secure circuits and methods of making same 有权
    用于安全电路的光学透明导线及其制造方法

    公开(公告)号：US08017514B2

    公开(公告)日：2011-09-13

    申请号：US12115056

    申请日：2008-05-05

    申请人： Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

    发明人： Stephen Peter Ayotte ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Kimball M. Watson

    IPC分类号： H01L21/00

    CPC分类号： H01L23/522 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76888 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

    摘要翻译： 一种结构和方法。 该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测 通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。

    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
    29.
    发明申请
    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 有权
    通过基板VIAS集成的金属接线结构

    公开(公告)号：US20110185330A1

    公开(公告)日：2011-07-28

    申请号：US13080716

    申请日：2011-04-06

    申请人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    发明人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    IPC分类号： G06F17/50

    CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

    摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。