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21.发明授权Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度公开(公告)号：US07598543B2
公开(公告)日：2009-10-06
申请号：US11438883
申请日：2006-05-23
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203
摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.
摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。
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22.发明授权Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译： 公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。 非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。 电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。 电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。
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公开(公告)号：US07208794B2
公开(公告)日：2007-04-24
申请号：US11073017
申请日：2005-03-04
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。
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24.发明授权Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor 失效场效应晶体管，电路结构和制造场效晶体管的方法公开(公告)号：US06740910B2
公开(公告)日：2004-05-25
申请号：US10352830
申请日：2003-01-28
IPC分类号： H01L2976
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/78642 , H01L51/0048 , H01L51/0052 , H01L51/0512 , Y10S977/938
摘要： The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain. The nanoelement may have the conductance thereof controlled by means of the gate, such that the nanoelement forms a channel region of the field effect transistor.
摘要翻译： 场效应晶体管的栅极区域包括至少一个通孔，其中提供了与源极和漏极电耦合的纳米元件。 纳米元件可以通过栅极控制其电导，使得纳米元件形成场效应晶体管的沟道区。
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25.发明授权Integrated circuit arrangement with low-resistance contacts and method for production thereof 有权具有低电阻触点的集成电路布置及其制造方法公开(公告)号：US07560351B2
公开(公告)日：2009-07-14
申请号：US11324803
申请日：2006-01-03
IPC分类号： H01L21/336
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/41725 , H01L29/665 , H01L29/78 , Y10S438/964
摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.
摘要翻译： 提出了一种集成电路布置和制造方法。 集成电路装置包含半导体和金属电极。 使用延伸穿过半导体和电极之间的过渡层的半导体和/或电极的部分区域，增加半导体和电极之间的接触面积而不增加横向尺寸。
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26.发明授权Semiconductor memory with vertical memory transistors and method for fabricating it 有权具有垂直存储晶体管的半导体存储器及其制造方法公开(公告)号：US07265413B2
公开(公告)日：2007-09-04
申请号：US11073205
申请日：2005-03-05
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.
摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。
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27.发明授权公开(公告)号：US07189988B2
公开(公告)日：2007-03-13
申请号：US10482719
申请日：2002-07-01
IPC分类号： H01L35/24
CPC分类号： G11C13/0019 , B82Y10/00 , G11C13/0014 , H01L51/0048 , H01L51/005 , H01L51/0052 , H01L51/0093 , H01L51/0595
摘要： The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.
摘要翻译： 本发明涉及一种分子电子装置，其包括基底，至少一个具有表面并且布置在基底中或基底上的第一条状导体，隔离物，其被布置在至少一个第一条状导体的表面上，并且部分覆盖 所述至少一个第一带状导体的表面和布置在所述间隔件上并包括以平面方式面对所述至少一个第一带状导体的表面的表面的至少一个第二条状导体。 所述间隔件部分地覆盖所述至少一个第二条状导体的表面，并且限定所述至少一个第一条状导体和所述至少一个第二条状导体之间的预定距离。 本发明的分子电子学装置还包括分子电子学分子，其分布在至少一个第一带状导体的表面的自由区域和至少一个第二条状导体的表面的自由区域之间，所述分子的长度为 基本上等于所述至少一个第一带状导体和所述至少一个第二带状导体之间的距离。 本发明还涉及生产分子电子装置的方法。
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28.发明授权Semiconductor memory with vertical memory transistors in a cell array arrangement with 1-2F2 cells 失效具有垂直存储晶体管的半导体存储器，其具有1-2F2个单元阵列公开(公告)号：US07075148B2
公开(公告)日：2006-07-11
申请号：US11073214
申请日：2005-03-05
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells, each of the memory cells having N (e.g., four) vertical memory transistors with trapping layers. Higher contact regions are formed in higher semiconductor regions extending obliquely with respect to the rows and columns of the cell array, the gate electrode generally being led to the step side areas of the higher semiconductor region. A storage density of 1-2F2 per bit can thus be achieved.
摘要翻译： 本发明涉及一种具有多个存储单元的半导体存储器，每个存储器单元具有N（例如四个）垂直存储晶体管，具有捕获层。 在相对于单元阵列的行和列倾斜地延伸的较高半导体区域中形成更高的接触区域，栅电极通常被引导到较高半导体区域的台阶侧区域。 因此可以实现每位1-2F 2的存储密度。
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29.发明授权公开(公告)号：US07719059B2
公开(公告)日：2010-05-18
申请号：US11588868
申请日：2006-10-27
IPC分类号： H01L21/84 , H01L21/8238 , H01L27/12
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785 , H01L29/78636
摘要： A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.
摘要翻译： 鳍状场效应晶体管布置包括衬底和衬底上和/或衬底中的第一鳍状场效应晶体管。 第一鳍状场效应晶体管包括鳍状物，其中在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域，并且在其上形成栅极区域。 第二鳍状场效应晶体管设置在衬底上和/或衬底中，包括在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域的鳍片，并且在其上形成栅极区域。 第二鳍状场效应晶体管沿第一鳍状场效应晶体管横向布置，其中第一鳍状场效应晶体管的鳍的高度大于第二鳍状场效应晶体管的鳍的高度。
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公开(公告)号：US06730930B2
公开(公告)日：2004-05-04
申请号：US10275598
申请日：2003-04-21
IPC分类号： H01L3524
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L51/0575
摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.
摘要翻译： 具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。 在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。 通道填充有填充材料，其电导率可以通过施加的电压而改变。
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