公开(公告)号：US07932155B2

公开(公告)日：2011-04-26

申请号：US11760288

申请日：2007-06-08

申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

IPC分类号： H01L21/8222

CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

公开(公告)号：US07262484B2

公开(公告)日：2007-08-28

申请号：US10908361

申请日：2005-05-09

申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

IPC分类号： H01L29/73

CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

公开(公告)号：US07135375B2

公开(公告)日：2006-11-14

申请号：US11053721

申请日：2005-02-08

申请人： Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

发明人： Douglas D. Coolbaugh ,  James S. Dunn ,  Michael D. Gordon ,  Mohamed Y. Hammad ,  Jeffrey B. Johnson ,  David C. Sheridan

IPC分类号： H01L21/20 ,  H01L21/8222

CPC分类号： H01L27/0811 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94

摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

公开(公告)号：US06869854B2

公开(公告)日：2005-03-22

申请号：US10064476

申请日：2002-07-18

申请人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L23/62

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

摘要： The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

摘要翻译： 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

公开(公告)号：US06809024B1

公开(公告)日：2004-10-26

申请号：US10249821

申请日：2003-05-09

申请人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

发明人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

IPC分类号： H01L2972

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

摘要： A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

公开(公告)号：US06420766B1

公开(公告)日：2002-07-16

申请号：US09368843

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US5631495A

公开(公告)日：1997-05-20

申请号：US346122

申请日：1994-11-29

申请人： James S. Dunn ,  Michael D. Hulvey ,  Eric D. Johnson ,  Robert A. Kertis ,  Kenneth K. Kieft, III ,  Albert E. Lanpher ,  Nicholas T. Schmidt

发明人： James S. Dunn ,  Michael D. Hulvey ,  Eric D. Johnson ,  Robert A. Kertis ,  Kenneth K. Kieft, III ,  Albert E. Lanpher ,  Nicholas T. Schmidt

IPC分类号： H01L21/331 ,  H01L23/482 ,  H01L29/423 ,  H01L27/082 ,  H01L29/167

CPC分类号： H01L29/66272 ,  H01L23/4824 ,  H01L29/42304 ,  H01L2924/0002 ,  Y10S148/01

摘要： High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

摘要翻译： 因此，阐述了具有改进的接线选项和制造方法的高性能双极晶体管。 双极晶体管包括具有多个接触焊盘的基极接触结构，当接线到晶体管时允许多个器件布局。 例如，第一器件布局可以包括集电极 - 基极 - 发射器器件布局，而第二器件布局可以包括集电极 - 发射极 - 器件布局。 更具体地，基部接触结构至少部分地围绕发射器并且具有远离发射极延伸的整体接触焊盘。 此外，基极接触结构的部分设置在晶体管的基极区域周围的绝缘层上，而其它部分直接接触基极区域。 因此，还提出了双极晶体管的具体细节以及制造方法。

公开(公告)号：US07303968B2

公开(公告)日：2007-12-04

申请号：US11299682

申请日：2005-12-13

申请人： James S. Dunn ,  Louis D. Lanzerotti ,  Steven H. Voldman

发明人： James S. Dunn ,  Louis D. Lanzerotti ,  Steven H. Voldman

IPC分类号： H01L21/8222 ,  H01L21/331 ,  H01L21/8249

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/0821

摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

摘要翻译： 提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。 子集电极可以使用不同剂量或不同的材料注入来提供，导致具有不同最佳单位电流增益截止频率（击穿电压）和击穿电压（BV＆lt; SUB> CBO ）。

公开(公告)号：US07265018B2

公开(公告)日：2007-09-04

申请号：US10711486

申请日：2004-09-21

申请人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

发明人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

公开(公告)号：US07064416B2

公开(公告)日：2006-06-20

申请号：US09991142

申请日：2001-11-16

申请人： James S. Dunn ,  Louis D. Lanzerotti ,  Steven H. Voldman

发明人： James S. Dunn ,  Louis D. Lanzerotti ,  Steven H. Voldman

IPC分类号： H01L27/082

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/0821

摘要： A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

摘要翻译： 提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。 子集电极可以使用不同剂量或不同的材料注入来提供，导致具有不同最佳单位电流增益截止频率（击穿电压）和击穿电压（BV＆lt; SUB> CBO ）。