中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.018 seconds)

    Mechanism for effectively handling texture sampling
    23.
    发明授权
    Mechanism for effectively handling texture sampling 有权
    有效处理纹理采样的机制

    公开(公告)号：US08933946B2

    公开(公告)日：2015-01-13

    申请号：US11967408

    申请日：2007-12-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G06T1/00 ,  G06T15/00 ,  G09G5/00 ,  G06F9/45 ,  G06T15/04 ,  G09G5/02

    CPC classification number: G09G5/00 ,  G06F8/41 ,  G06T15/005 ,  G06T15/04 ,  G06T2200/28 ,  G09G5/026 ,  G09G2340/10 ,  G09G2360/121

    Abstract: A method and apparatus for efficiently handling texture sampling is described herein. A compiler or other software is capable of breaking a texture sampling operation for a pixel into a pre-fetch operation and a use operation. A processing element, in response to executing the pre-fetch operation, delegates computation of the texture sample of the pixel to a hardware texture sample unit. In parallel to the hardware texture sample unit performing a texture sample for the pixel and providing the result, i.e. a textured pixel (texel), to a destination address, the processing element is capable of executing other independent code. After an amount of time, the processing element executes the use operation, such as a load operation to load the texel from the destination address.

    Abstract translation: 本文描述了一种用于有效处理纹理采样的方法和装置。 编译器或其他软件能够将像素的纹理采样操作分解成预取操作和使用操作。 响应于执行预取操作，处理元件将像素的纹理样本的计算委托给硬件纹理采样单元。 与硬件纹理采样单元平行地执行像素的纹理样本并将结果（即，纹理像素（纹素））提供给目的地址，处理元件能够执行其他独立代码。 在一段时间之后，处理元件执行使用操作，例如从目的地地址加载纹素的加载操作。

    Unaligned memory operands
    28.
    发明授权
    Unaligned memory operands 有权
    未对齐的内存操作数

    公开(公告)号：US06721866B2

    公开(公告)日：2004-04-13

    申请号：US10029367

    申请日：2001-12-21

    Applicant: Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

    Inventor： Patrice Roussel ,  Eric Sprangle ,  Glenn J. Hinton

    IPC: G06F1204

    CPC classification number: G06F9/30043

    Abstract: A method of obtaining an operand from a memory device includes reading a first operand from a first location in a memory device, the first operand including part of the operand specified by an instruction, shifting the first operand by a first shift amount, reading a second data operand from the memory device, the second operand having part of the operand specified by the instruction, shifting the second operand by a second shift amount, and combining the first shifted data entry and the second shifted data entry to produce an aligned operand, wherein shifting the first operand and shifting the second operand is performed by a shifter also used for floating point functions.

    Abstract translation: 从存储装置获取操作数的方法包括从存储装置中的第一位置读取第一操作数，第一操作数包括由指令指定的操作数的一部分，将第一操作数移位第一移位量，读第二操作数 来自存储器件的数据操作数，第二操作数具有由指令指定的操作数的一部分，将第二操作数移位第二移位量，并组合第一移位数据条目和第二移位数据条目以产生对准的操作数，其中 移动第一操作数并移动第二操作数由也用于浮点函数的移位器执行。

    Partition-free multi-socket memory system architecture
    29.
    发明授权
    Partition-free multi-socket memory system architecture 有权
    无分区多插槽内存系统架构

    公开(公告)号：US08605099B2

    公开(公告)日：2013-12-10

    申请号：US12059193

    申请日：2008-03-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G06F13/00

    CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

    Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

    Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。

Patent Agency Ranking