公开(公告)号：US20100237425A1

公开(公告)日：2010-09-23

申请号：US12727312

申请日：2010-03-19

申请人： Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

发明人： Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823412

摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

摘要翻译： 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

公开(公告)号：US07521376B2

公开(公告)日：2009-04-21

申请号：US11259165

申请日：2005-10-26

申请人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

发明人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

IPC分类号： H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

摘要翻译： 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长过程中和之后不希望的界面化合物的形成，并且界面陷阱的密度降低。

公开(公告)号：US07449782B2

公开(公告)日：2008-11-11

申请号：US10838378

申请日：2004-05-04

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L29/40

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20080227283A1

公开(公告)日：2008-09-18

申请号：US12108001

申请日：2008-04-23

申请人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/28

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种在与由纯金属形成的常规硅化物接触相比更耐蚀刻性的Ge含有层上方形成硅锗化物的方法。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20070093074A1

公开(公告)日：2007-04-26

申请号：US11259165

申请日：2005-10-26

申请人： Martin Frank ,  Steven Koester ,  John Ott ,  Huiling Shang

发明人： Martin Frank ,  Steven Koester ,  John Ott ,  Huiling Shang

IPC分类号： H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

摘要翻译： 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长期间和之后不期望的界面化合物的形成，并且界面陷阱的密度降低。

公开(公告)号：US08685818B2

公开(公告)日：2014-04-01

申请号：US12823168

申请日：2010-06-25

申请人： Huiling Shang ,  Ying Li ,  Henry K. Utomo

发明人： Huiling Shang ,  Ying Li ,  Henry K. Utomo

IPC分类号： H01L29/8605

CPC分类号： H01L28/20 ,  H01L21/76229 ,  H01L27/0629

摘要： Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.

摘要翻译： 在分离两个相邻器件的有源区域的浅沟槽隔离件之间形成多晶硅嵌入式电阻器，最小化两个器件之间的电气相互作用，并减少它们之间的电容耦合或泄漏。 当多晶硅电阻器嵌入STI凹陷区域内时，通过在STI区域内形成凹陷区域，独立于形成栅电极而形成精密多晶硅电阻器。 多晶硅电阻器与栅极电极分离，使其免受与栅电极相关的工艺的影响。 该方法在形成STI之后但在形成p阱和n阱注入之前形成多晶硅电阻器。 在另一个实施例中，在形成STI之后但在形成井注入之后形成电阻器。

公开(公告)号：US20130161763A1

公开(公告)日：2013-06-27

申请号：US13332991

申请日：2011-12-21

申请人： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

发明人： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78621

摘要： A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.

摘要翻译： 一种方法包括在半导体的表面上形成由插头构成的虚拟栅极结构; 形成围绕所述插塞的第一间隔件，所述第一间隔件是牺牲间隔件; 以及执行成角度的离子注入，以便将掺杂剂物质注入与所述第一间隔物的外侧壁相邻的所述半导体的表面中，以形成源延伸区域和漏极延伸区域，其中所述注入的掺杂剂物质在所述外侧壁 的第一间隔物的量是离子注入的角度的函数。 该方法还包括执行激光退火以激活源延伸和漏极延伸植入。 该方法还包括形成围绕第一间隔件的第二间隔件，去除第一间隔件和插塞以形成开口，以及在开口中沉积栅极堆叠。

公开(公告)号：US07682968B2

公开(公告)日：2010-03-23

申请号：US12108001

申请日：2008-04-23

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/44

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20080248616A1

公开(公告)日：2008-10-09

申请号：US12118689

申请日：2008-05-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/8238 ,  H01L21/335

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

公开(公告)号：US07387925B2

公开(公告)日：2008-06-17

申请号：US11799261

申请日：2007-04-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

摘要翻译： 公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。