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146 条记录 (耗时 0.027 秒)

    Forming phase change memory cell with microtrenches
    21.
    发明申请
    Forming phase change memory cell with microtrenches 审中-公开
    形成具有微通道的相变记忆体

    公开(公告)号：US20060097341A1

    公开(公告)日：2006-05-11

    申请号：US10982295

    申请日：2004-11-05

    申请人： Fabio Pellizzer ,  Charles Dennison

    发明人： Fabio Pellizzer ,  Charles Dennison

    IPC分类号： H01L29/00 ,  H01L21/477

    CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.

    摘要翻译： 半导体衬底被电介质区域覆盖。 电介质区域容纳存储元件和形成相变存储单元的选择元件。 存储元件由电阻元件和在接触区域上延伸并与电阻元件接触的相变材料的存储区域形成。 选择元件由嵌入在电介质区域中的属于在电阻元件上延伸并且还包括存储区域的堆叠的金属的切换区域形成。 模具区域在电阻元件的顶部延伸并限定具有基本细长形状的沟槽。 存储区域的至少一部分在沟槽中延伸并限定了接触区域上的相变存储部分。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    22.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    用于制造Cu-镶嵌技术中的相变存储器阵列的方法和由其制造的相变存储器阵列

    公开(公告)号：US20050064606A1

    公开(公告)日：2005-03-24

    申请号：US10902508

    申请日：2004-07-29

    申请人： Fabio Pellizzer ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Roberto Bez

    IPC分类号： H01L27/24 ,  H01L21/00

    CPC分类号： H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

    摘要翻译： 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。

    Field programmable gate array device
    23.
    发明申请
    Field programmable gate array device 有权
    现场可编程门阵列器件

    公开(公告)号：US20050062497A1

    公开(公告)日：2005-03-24

    申请号：US10948079

    申请日：2004-09-23

    申请人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    IPC分类号： G11C16/02 ,  G11C16/04 ,  H03K3/037 ,  H03K19/177

    CPC分类号： G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    摘要翻译： 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

    MEMORY DEVICE WITH DOUBLE PROTECTIVE LINER
    25.
    发明申请
    MEMORY DEVICE WITH DOUBLE PROTECTIVE LINER 审中-公开

    公开(公告)号：US20200286957A1

    公开(公告)日：2020-09-10

    申请号：US16295687

    申请日：2019-03-07

    申请人： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

    发明人： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

    IPC分类号： H01L27/24 ,  H01L23/528 ,  H01L45/00

    摘要： A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

    Memory arrays and methods of forming memory cells
    28.
    发明授权
    Memory arrays and methods of forming memory cells 有权

    公开(公告)号：US08546231B2

    公开(公告)日：2013-10-01

    申请号：US13298962

    申请日：2011-11-17

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    IPC分类号： G11C17/16

    CPC分类号： H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

    摘要： Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.