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342 条记录 (耗时 0.035 秒)

    Memory system and method for strobing data, command and address signals
    21.
    发明授权
    Memory system and method for strobing data, command and address signals 有权

    公开(公告)号：US07187617B2

    公开(公告)日：2007-03-06

    申请号：US11351836

    申请日：2006-02-10

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

    摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

    Fast-locking digital phase locked loop
    22.
    发明申请
    Fast-locking digital phase locked loop 有权
    快速锁定数字锁相环

    公开(公告)号：US20060202726A1

    公开(公告)日：2006-09-14

    申请号：US11388226

    申请日：2006-03-23

    申请人： Feng Lin ,  Brent Keeth

    发明人： Feng Lin ,  Brent Keeth

    IPC分类号： H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/0814

    摘要： An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

    摘要翻译： 一种用于同步信号的装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

    Fast-locking digital phase locked loop
    23.
    发明申请
    Fast-locking digital phase locked loop 有权
    快速锁定数字锁相环

    公开(公告)号：US20060033542A1

    公开(公告)日：2006-02-16

    申请号：US10915774

    申请日：2004-08-11

    申请人： Feng Lin ,  Brent Keeth

    发明人： Feng Lin ,  Brent Keeth

    IPC分类号： H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/0814

    摘要： A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

    摘要翻译： 一种用于同步信号的方法和装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

    Method and system for delay control in synchronization circuits
    24.
    发明授权
    Method and system for delay control in synchronization circuits 失效
    同步电路延时控制方法与系统

    公开(公告)号：US06836166B2

    公开(公告)日：2004-12-28

    申请号：US10339752

    申请日：2003-01-08

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson

    IPC分类号： H03L706

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.

    摘要翻译： 同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。 每个移相路径电路响应于控制信号调整粗略和精细的相移。 选择电路响应于选择信号输出一个相移信号。 控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细 和另一路径电路的粗相移。 当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。

    WAFER-SCALE MEMORY TECHNIQUES
    25.
    发明申请
    WAFER-SCALE MEMORY TECHNIQUES 有权

    公开(公告)号：US20210240344A1

    公开(公告)日：2021-08-05

    申请号：US17162796

    申请日：2021-01-29

    申请人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    发明人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    IPC分类号： G06F3/06

    摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

    MEMORY DEVICE INTERFACE AND METHOD
    26.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 有权

    公开(公告)号：US20210200464A1

    公开(公告)日：2021-07-01

    申请号：US17136728

    申请日：2020-12-29

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G06F3/06

    摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    29.
    发明申请
    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
    基于命令信号和操作状态解码命令的系统和方法

    公开(公告)号：US20120246434A1

    公开(公告)日：2012-09-27

    申请号：US13489246

    申请日：2012-06-05

    申请人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F12/00

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。