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235 条记录 (耗时 0.032 秒)

    Nonvolatile semicondutor memory device and manufacturing method thereof
    22.
    发明申请
    Nonvolatile semicondutor memory device and manufacturing method thereof 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20110287597A1

    公开(公告)日：2011-11-24

    申请号：US13064559

    申请日：2011-03-31

    申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

    摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

    摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    25.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20080315296A1

    公开(公告)日：2008-12-25

    申请号：US12142289

    申请日：2008-06-19

    申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/11556

    摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

    摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

    Semiconductor memory with trench capacitor and method of fabricating the same
    27.
    发明申请
    Semiconductor memory with trench capacitor and method of fabricating the same 失效
    具有沟槽电容器的半导体存储器及其制造方法

    公开(公告)号：US20050184323A1

    公开(公告)日：2005-08-25

    申请号：US11038173

    申请日：2005-01-21

    申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

    发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

    CPC分类号： H01L27/10867

    摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor adjacently formed to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

    摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，与沟槽电容器相邻形成并具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域的单元晶体管， 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区域之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

    Semiconductor device and method for manufacturing the same
    29.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08847303B2

    公开(公告)日：2014-09-30

    申请号：US13422294

    申请日：2012-03-16

    申请人： Masaru Kito ,  Ryota Katsumata

    发明人： Masaru Kito ,  Ryota Katsumata

    IPC分类号： H01L29/792 ,  H01L27/115

    CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582

    摘要： According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.

    摘要翻译： 根据一个实施例，半导体器件包括：衬底; 设置在所述基板上方的堆叠体，包括设置在所述选择器门上的选择栅和绝缘层; 设置在沿层叠方向穿过层叠体而形成的孔的侧壁上的绝缘膜; 通道体和半导体层。 通道体设置在孔中的绝缘膜的侧壁上，其阻挡在选择栅中的绝缘层侧的端部附近的孔，并且在封闭孔的部分下方包围空腔。 半导体层由与沟道体相同的材料形成，并且被连续地嵌入在通道体阻挡孔的部分上方的孔中。

    Nonvolatile semiconductor memory device and method of data write therein
    30.
    发明授权
    Nonvolatile semiconductor memory device and method of data write therein 有权
    非易失性半导体存储器件及其中的数据写入方法

    公开(公告)号：US08760924B2

    公开(公告)日：2014-06-24

    申请号：US13427263

    申请日：2012-03-22

    申请人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    发明人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

    摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

    摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。