公开(公告)号：US11069772B2

公开(公告)日：2021-07-20

申请号：US16221034

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

公开(公告)号：US20150144960A1

公开(公告)日：2015-05-28

申请号：US14091622

申请日：2013-11-27

Applicant: General Electric Company

Inventor： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/4933 ,  H01L21/0273 ,  H01L21/049 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7802

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Abstract translation: 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。在一个实施例中，半导体器件包括设置在 半导体层顶部。 半导体器件还包括具有锥形侧壁的栅电极。 此外，栅极包括设置在栅极氧化物层的顶部上的多晶硅层和设置在多晶硅层顶部的金属硅化物层。

公开(公告)号：US12191384B2

公开(公告)日：2025-01-07

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11764257B2

公开(公告)日：2023-09-19

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11538769B2

公开(公告)日：2022-12-27

申请号：US16220979

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Liangchun Yu ,  Nancy Cecelia Stoffel ,  David Richard Esler ,  Christopher James Kapusta

IPC: H01L23/60 ,  H01L29/06 ,  H01L29/16 ,  H01L23/00

Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

公开(公告)号：US11417759B2

公开(公告)日：2022-08-16

申请号：US16433809

申请日：2019-06-06

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L29/49 ,  H01L29/739 ,  H01L29/745 ,  H01L23/04 ,  H01L21/50

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

公开(公告)号：US11056586B2

公开(公告)日：2021-07-06

申请号：US16147216

申请日：2018-09-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almem Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US10903330B2

公开(公告)日：2021-01-26

申请号：US14091622

申请日：2013-11-27

Applicant: General Electric Company

Inventor： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L21/3213 ,  H01L21/027

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

公开(公告)号：US20160307997A1

公开(公告)日：2016-10-20

申请号：US15194774

申请日：2016-06-28

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Motocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljuibisa Dragolijub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/36 ,  H01L21/04

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.

Abstract translation: 半导体器件可以包括包含碳化硅的衬底; 设置在掺杂有第一掺杂剂类型的衬底上的漂移层; 邻近所述漂移层设置的阳极区域，其中所述阳极区域掺杂有第二掺杂剂类型; 以及连接终端延伸部，其邻近所述阳极区域设置并且围绕所述阳极区域延伸，其中所述连接终端延伸部具有宽度并且包括在第一方向和第二方向上分离的多个离散区域，并且以 第二掺杂剂类型，以便具有通常沿着远离主阻塞结的边缘的方向减小的功能形式的第二导电类型的有效掺杂分布。

公开(公告)号：US09406762B2

公开(公告)日：2016-08-02

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。