公开(公告)号：US20180233417A1

公开(公告)日：2018-08-16

申请号：US15956082

申请日：2018-04-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L27/092 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US20180122711A1

公开(公告)日：2018-05-03

申请号：US15847028

申请日：2017-12-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

发明人： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768

CPC分类号： H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US09755031B2

公开(公告)日：2017-09-05

申请号：US14577431

申请日：2014-12-19

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

发明人： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

公开(公告)号：US20170178967A1

公开(公告)日：2017-06-22

申请号：US15359953

申请日：2016-11-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

发明人： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L27/088

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09660083B2

公开(公告)日：2017-05-23

申请号：US14560255

申请日：2014-12-04

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

发明人： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

摘要： A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

公开(公告)号：US20170053982A1

公开(公告)日：2017-02-23

申请号：US15340491

申请日：2016-11-01

申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065

CPC分类号： H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

摘要： Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

摘要翻译： 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。

公开(公告)号：US20170005014A1

公开(公告)日：2017-01-05

申请号：US14789476

申请日：2015-07-01

申请人： International Business Machines Corporation ,  Globalfoundries, Inc.

发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC分类号： H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L22/32 ,  H01L21/76895 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

摘要翻译： 实施例涉及一种方法。实施例涉及鳍式场效应晶体管（FinFET）的测试结构。 测试结构包括电耦合到FinFET的伪栅极的第一导电层和电耦合到FinFET的衬底的第二导电层。 测试结构还包括电耦合到FinFET的伪栅极的第三导电层，以及至少部分地由第一导电层和第二导电层限制的FinFET的第一区域。 所述测试结构还包括至少部分地由所述第二导电层和所述第三导电层限制的所述FinFET的第二区域，其中所述第一区域包括具有第一尺寸的第一电介质，并且其中所述第二区域包括具有 第二维度大于第一维度。

公开(公告)号：US20160365411A1

公开(公告)日：2016-12-15

申请号：US14739543

申请日：2015-06-15

申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Chun-Chen Yeh ,  Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/66

CPC分类号： H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

摘要： Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

摘要翻译： 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。

公开(公告)号：US20160293494A1

公开(公告)日：2016-10-06

申请号：US15180158

申请日：2016-06-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

摘要： A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

公开(公告)号：US09306001B1

公开(公告)日：2016-04-05

申请号：US14685745

申请日：2015-04-14

申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

摘要翻译： 实施例涉及一种形成鳍式场效应晶体管（FinFET）的漏电流阻挡器的方法。 该方法包括在有源区中形成至少一个具有有源区，非有源区和沟道区的鳍。 该方法还包括暴露非有源区的表面，其中暴露的表面导致基本上在沟道区下面的非有源区的一部分。 该方法还包括通过非有源区的暴露表面注入掺杂剂以形成泄漏电流停止区。