公开(公告)号：US10522639B2

公开(公告)日：2019-12-31

申请号：US16458056

申请日：2019-06-29

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC分类号： H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/225 ,  H01L21/321 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238

摘要： At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US20190280114A1

公开(公告)日：2019-09-12

申请号：US15919079

申请日：2018-03-12

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Xusheng Wu ,  Haigou Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

摘要： Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10373875B1

公开(公告)日：2019-08-06

申请号：US15928783

申请日：2018-03-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/311 ,  H01L21/762

摘要： Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US20180366461A1

公开(公告)日：2018-12-20

申请号：US15627835

申请日：2017-06-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/66

CPC分类号： H01L27/0629 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L28/20 ,  H01L28/24 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851

摘要： One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.

公开(公告)号：US09711624B1

公开(公告)日：2017-07-18

申请号：US15074235

申请日：2016-03-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Fang Fang ,  Daniel Jaeger

IPC分类号： H01L23/58 ,  H01L29/66 ,  H01L21/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/78

CPC分类号： H01L29/6681 ,  G03F7/70616 ,  G03F7/70683 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/20 ,  H01L29/7851

摘要： Methods and apparatus for measuring pitch-walking are disclosed. Embodiments include forming parallel, spaced mandrels in test sites on a substrate; performing two SIT processes, forming first-fourth fins in the substrate for each mandrel; designating spaces between first and second and between third and fourth fins as β, between first and fourth fins of adjacent mandrels as α, and between second and third fins as γ in each test site; applying a first lithomask over fins at a first test site selecting spaces designated as one of α, β, or γ and the adjacent fins; applying a second lithomask over fins at a second test site selecting second spaces, designated as a different one of α, β, or γ and the adjacent fins; measuring the selected first and second spaces; determining differences between the measured first and second spaces; and adjusting processes for forming fins based on the differences.