公开(公告)号：US10395981B2

公开(公告)日：2019-08-27

申请号：US15793253

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Jeremy Austin Wahl

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/04

Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

公开(公告)号：US20190122921A1

公开(公告)日：2019-04-25

申请号：US15793253

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Jeremy Austin Wahl

IPC: H01L21/768 ,  H01L29/04

CPC classification number: H01L21/76822 ,  H01L21/28052 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/045 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

公开(公告)号：US09960184B2

公开(公告)日：2018-05-01

申请号：US15645686

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L29/94 ,  H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786 ,  H01L49/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/285 ,  H01L27/108

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09673115B2

公开(公告)日：2017-06-06

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L29/10 ,  H01L21/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US20170133287A1

公开(公告)日：2017-05-11

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L21/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US09627409B2

公开(公告)日：2017-04-18

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L21/76 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8258

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

公开(公告)号：US20170062438A1

公开(公告)日：2017-03-02

申请号：US15146979

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L27/11 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/4958 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device is provided including forming a gate electrode layer over a semiconductor substrate, forming a sidewall spacer at a sidewall of the gate electrode layer, forming a raised source/drain region over the semiconductor substrate and adjacent to the sidewall spacer, removing a portion of the sidewall spacer, thereby exposing a portion of the sidewall of the gate electrode layer, and forming an electrically conductive layer electrically connecting the exposed portion of the sidewall of the gate electrode layer and the source/drain region.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体衬底上形成栅电极层，在栅极电极层的侧壁处形成侧壁间隔物，在半导体衬底上形成凸起的源极/漏极区域，并且邻近于侧壁间隔物 去除所述侧壁间隔物的一部分，从而暴露所述栅电极层的侧壁的一部分，以及形成电连接所述栅极电极层的侧壁的暴露部分和所述源极/漏极区域的导电层。

公开(公告)号：US20160300856A1

公开(公告)日：2016-10-13

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/538 ,  H01L21/8258 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

Abstract translation: 提供一种具有含金属层的半导体器件，形成在含金属层顶部的第一半导体层和形成在含金属层中并与第一半导体层接触的电阻器 。 此外，提供了一种制造半导体器件的方法，其中该方法包括制造电阻器，具体步骤如下：在晶片上，特别是SOI晶片上形成含金属层，在第一半导体层上形成第一半导体层 含金属层和通过半导体层形成与含金属层的接触。

公开(公告)号：US09425189B1

公开(公告)日：2016-08-23

申请号：US14813292

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L27/01 ,  H01L31/0392 ,  H01L27/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L21/02 ,  H01L29/417 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/743 ,  H01L21/823418 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78603

Abstract: The present disclosure provides a semiconductor device including an SOI substrate comprising an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base semiconductor material. The semiconductor device further includes a gate structure formed on the active semiconductor layer, source/drain regions provided at opposing sides of the gate structure, and a contact structure having contact elements for contacting the source/drain regions. Herein, the contact elements are disposed at opposing sides of the gate structure and are in alignment therewith. Furthermore, one of the contact elements extends through the buried insulating material layer and is in electrical contact with the base semiconductor material.

Abstract translation: 本公开提供了一种包括SOI衬底的半导体器件，SOI衬底包括设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基极半导体材料上。 半导体器件还包括形成在有源半导体层上的栅极结构，设置在栅极结构的相对侧处的源极/漏极区域和具有用于接触源极/漏极区域的接触元件的接触结构。 这里，接触元件设置在栅极结构的相对侧并且与其对准。 此外，一个接触元件延伸穿过掩埋绝缘材料层并与基底半导体材料电接触。

公开(公告)号：US09385232B2

公开(公告)日：2016-07-05

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。