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    Application specific integrated circuit (ASIC) test screens and selection of such screens
    22.
    发明申请
    Application specific integrated circuit (ASIC) test screens and selection of such screens 有权

    公开(公告)号：US20170220727A1

    公开(公告)日：2017-08-03

    申请号：US15012331

    申请日：2016-02-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/64

    Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

    Content-addressable memory having multiple reference matchlines to reduce latency
    23.
    发明授权
    Content-addressable memory having multiple reference matchlines to reduce latency 有权

    公开(公告)号：US09704575B1

    公开(公告)日：2017-07-11

    申请号：US14990125

    申请日：2016-01-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle ,  Thomas M. Maffitt

    IPC: G11C7/00 ,  G11C15/04

    CPC classification number: G11C15/04

    Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.

    Bending circuit for static random access memory (SRAM) self-timer
    24.
    发明授权
    Bending circuit for static random access memory (SRAM) self-timer 有权

    公开(公告)号：US10217507B2

    公开(公告)日：2019-02-26

    申请号：US15345544

    申请日：2016-11-08

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Venkatraghavan Bringivijayaraghavan ,  Sreejith Chidambaran ,  Igor Arsovski

    IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22

    Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

    BENDING CIRCUIT FOR STATIC RANDOM ACCESS MEMORY (SRAM) SELF-TIMER
    25.
    发明申请
    BENDING CIRCUIT FOR STATIC RANDOM ACCESS MEMORY (SRAM) SELF-TIMER 审中-公开

    公开(公告)号：US20180130521A1

    公开(公告)日：2018-05-10

    申请号：US15345544

    申请日：2016-11-08

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Venkatraghavan Bringivijayaraghavan ,  Sreejith Chidambaran ,  Igor Arsovski

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/22

    Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

    Application specific integrated circuit (ASIC) test screens and selection of such screens
    27.
    发明授权
    Application specific integrated circuit (ASIC) test screens and selection of such screens 有权

    公开(公告)号：US09760673B2

    公开(公告)日：2017-09-12

    申请号：US15012331

    申请日：2016-02-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/64

    Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

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