公开(公告)号：US20190131406A1

公开(公告)日：2019-05-02

申请号：US15797606

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed that extend vertically from a top surface of a substrate. A body region is arranged partially in the substrate and partially in the first fin. A drain region is arranged partially in the substrate, partially in the first fin, and partially in the second fin. The body and drain regions respectively have opposite first and second conductivity types. A source region of the second conductivity type is located within the first well in the first fin, and a gate structure is arranged to overlap with a portion of the first fin. The first fin is separated from the second fin by a cut extending vertically to the top surface of the substrate. An isolation region is arranged in the cut between the first fin and the second fin.

公开(公告)号：US10163915B1

公开(公告)日：2018-12-25

申请号：US15634227

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.

公开(公告)号：US10134739B1

公开(公告)日：2018-11-20

申请号：US15661058

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/115 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/28

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US09773781B1

公开(公告)日：2017-09-26

申请号：US15342498

申请日：2016-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jagar Singh ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate. A gate structure is disposed over the substrate. The gate structure includes: a pair of gate spacers extending generally vertically from the substrate, gate metal disposed between the spacers, and a self-aligned contact (SAC) cap disposed over the gate metal to form a top of the gate structure. A first capacitor plate is disposed directly upon the SAC cap such that no additional layer is disposed between the resistor and SAC cap. An insulator layer and a second capacitor plate are disposed on the first capacitor plate forming a MIM capacitor. A pair of capacitor plate contacts are electrically connected to the first capacitor plate and the second capacitor plate.

公开(公告)号：US09543298B1

公开(公告)日：2017-01-10

申请号：US15067455

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0273 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of forming a single diffusion break includes etching rows of fins into a substrate of a structure from a patterned fin hardmask, the remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the structure to expose the fin hardmask. A photoresist layer is disposed over the structure. An isolation region is patterned across the fins to form first and second parallel fin arrays, wherein any remaining photoresist layer has self-aligned edges which are self-aligned with the isolation region. The self-aligned edges are trimmed to expose end portions of the fin hardmask. The exposed end portions are removed. The remaining photoresist layer is removed. A second dielectric fill material is disposed and planarized over the structure to form a base for a single diffusion break (SDB) in the isolation region.

Abstract translation: 形成单个扩散断裂的方法包括从图案化散热片硬掩模将排成一排散热片蚀刻成结构的基板，剩余的散热片硬掩模与散热片自对准。 在结构上设置和平坦化第一介电填充材料以暴露散热片硬掩模。 光致抗蚀剂层设置在结构上。 隔离区跨越翅片形成图案以形成第一和第二平行翅片阵列，其中任何残留的光致抗蚀剂层具有与隔离区自对准的自对准边缘。 自对准边缘被修剪以暴露散热片硬掩模的端部。 露出的端部被去除。 去除剩余的光致抗蚀剂层。 第二介电填充材料在结构上设置和平坦化，以形成隔离区域中的单个扩散断裂（SDB）的基底。

公开(公告)号：US09202911B2

公开(公告)日：2015-12-01

申请号：US13912448

申请日：2013-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure.

Abstract translation: 一个说明性器件包括形成在衬底中的源极区域和漏极区域，其中源极/漏极区域掺杂有第一类型的掺杂剂材料，位于衬底上方的栅极结构，该栅极结构横向地位于源极区域和漏极 区域和位于衬底中的漏极侧阱区域，其位于漏极区域的整个横向宽度的部分但不是全部，其中漏极侧阱区域还掺杂有第一类型的掺杂剂材料。 该器件还包括源极侧阱区域，其位于源极区域的整个宽度的整个宽度之下且在漏极区域的一部分但不是全部的位置处，并且漏极区域的延伸部分的一部分位于 部分门结构。

公开(公告)号：US09087706B2

公开(公告)日：2015-07-21

申请号：US14580834

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/735

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

公开(公告)号：US20140302660A1

公开(公告)日：2014-10-09

申请号：US13856542

申请日：2013-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Jerome Ciavatti

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76895 ,  H01L27/0255

Abstract: Embodiments disclosed describe approaches for providing a local interconnection between a protection diode and a gate transistor in an integrated circuit (IC) device. Specifically, described is an IC device comprising: a protection diode formed in a substrate, a replacement metal gate (RMG) transistor formed over the substrate, a first contact formed over the protection diode (and optional trench silicide layer), a second contact formed over the RMG transistor, wherein the first contact extends to connect directly with the second contact, and a top metal layer (M1) formed over the first contact and the second contact. By extending the first contact from the protection diode directly to the gate transistor as a supplemental interconnect, any charges accumulated during formation of the second contact and the set of vias will be discharged by the protection diode.

Abstract translation: 公开的实施例描述了在集成电路（IC）装置中提供保护二极管和栅极晶体管之间的局部互连的方法。 具体地，描述了一种IC器件，包括：形成在衬底中的保护二极管，在衬底上形成的替代金属栅极（RMG）晶体管，形成在保护二极管（和可选的沟槽硅化物层）上方的第一接触，形成的第二接触 在所述RMG晶体管上，其中所述第一触点延伸以直接与所述第二触点连接，以及形成在所述第一触点和所述第二触点上的顶部金属层（M1）。 通过将第一接触从保护二极管直接延伸到栅极晶体管作为补充互连，在形成第二接触和通孔组期间累积的任何电荷将被保护二极管放电。

公开(公告)号：US20140103420A1

公开(公告)日：2014-04-17

申请号：US13650233

申请日：2012-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Vara Vakada ,  Jerome Ciavatti

IPC: H01L29/78

CPC classification number: H01L23/5225 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract translation: 本文公开的一种说明性器件包括晶体管，其包括形成在半导体衬底中的栅电极和漏区，形成在衬底中的隔离结构，其中隔离结构横向地位于栅电极和漏区之间，法拉第屏蔽 其位于栅极电极和漏极区域之间并且隔离结构之上，其中法拉第屏蔽具有相对于衬底的上表面基本垂直取向的长轴。

公开(公告)号：US10418365B2

公开(公告)日：2019-09-17

申请号：US16111263

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.