公开(公告)号：US20140327146A1

公开(公告)日：2014-11-06

申请号：US13874803

申请日：2013-05-01

Applicant: Globalfoundries Inc

Inventor： Yunfei Deng ,  Lei Yuan ,  Hidekazu Yoshida ,  Juhan Kim ,  Mahbub Rashed ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/48

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Abstract translation: 公开了用于集成电路布线的设计方法。 该方法包括放置具有双扩散断裂的电池，这产生扩展的电池间​​区域。 金属层禁止区被定义为禁止禁区内的任何M1结构。 金属层允许区域邻近外部金属线放置，并且在金属层中形成点动允许区域。 然后将通风口和viabars应用于慢跑。

公开(公告)号：US08843869B1

公开(公告)日：2014-09-23

申请号：US13838378

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry Levinson

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.

Abstract translation: 公开了一种用于插入通孔的方法和装置，其改善了所得到的装置的可制造性，同时确保符合DRC规则。 实施例包括：确定具有第一通孔和多个路线的IC设计的基板的层，所述多个路线在基板上水平延伸并且放置在多个等间隔的垂直位置中的一个上; 比较在多个路线的第一组之间垂直延伸并且在第二组多个路线之间水平延伸的层的区域与一个或多个阈值，所述区域与第一通孔相邻并且与第一通孔分离 多条路线; 以及基于所述比较来插入第二通孔。

公开(公告)号：US08839168B2

公开(公告)日：2014-09-16

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Harry J Levinson ,  Jason E Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。

公开(公告)号：US20140225270A1

公开(公告)日：2014-08-14

申请号：US13766141

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei YUAN ,  Jongwook Kye ,  Harry Levinson

IPC: H01L21/308 ,  H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。

公开(公告)号：US10347546B2

公开(公告)日：2019-07-09

申请号：US15389632

申请日：2016-12-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Wenhui Wang ,  Xuelian Zhu ,  Jongwook Kye

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L21/84 ,  H01L27/12 ,  H01L23/485 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/088

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

公开(公告)号：US10204861B2

公开(公告)日：2019-02-12

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian Zhu ,  Jia Zeng ,  Wenhui Wang ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

公开(公告)号：US20180102354A1

公开(公告)日：2018-04-12

申请号：US15289401

申请日：2016-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Wang ,  Jia Zeng ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jongwook Kye

IPC: H01L27/02 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L21/76838

Abstract: At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

公开(公告)号：US20170323902A1

公开(公告)日：2017-11-09

申请号：US15149066

申请日：2016-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jia Zeng ,  Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/528 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/768 ,  H01L27/105 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L2027/11875

Abstract: At least one method, apparatus and system disclosed involves circuit layout for comprising a unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.

公开(公告)号：US09727685B2

公开(公告)日：2017-08-08

申请号：US14712830

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Yan Wang ,  Chenchen Wang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

公开(公告)号：US09437481B2

公开(公告)日：2016-09-06

申请号：US14674792

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jia Zeng ,  Youngtag Woo ,  Jongwook Kye

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/76802 ,  H01L21/027 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.

Abstract translation: 一种方法包括在硬掩模层之上形成心轴元件，在心轴元件上形成第一和第二间隔物，去除心轴元件，限定在第一和第二间隔物之间​​的第一开口，并暴露硬掩模层的一部分并具有 沿第一方向延伸的纵轴，形成覆盖所述第一开口的中间部分的阻挡掩模，所述阻挡掩模具有在与所述第一方向不同的第二方向上延伸的纵向轴线;在所述阻挡掩模的存在下， 阻挡掩模和所述第一和第二间隔物，以限定在所述硬掩模层中沿所述第一方向延伸的对准的第一和第二线段开口，基于所述第一和第二线段开口蚀刻设置在所述硬掩模层下方的电介质层中的凹陷， 并用导电材料填充凹部。