公开(公告)号：US09349718B2

公开(公告)日：2016-05-24

申请号：US14469155

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract translation: 这里提出了配置为ESD保护装置的场效应晶体管（FET）。 在一个实施例中，FET可以被配置为以快速恢复操作模式操作。 FET可以包括半导体衬底，形成在衬底上的栅极和形成在与栅极间隔开的衬底上的伪栅极。

公开(公告)号：US20160126239A1

公开(公告)日：2016-05-05

申请号：US14928272

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jagar Singh ,  Sanford Chu

IPC: H01L27/06 ,  H01L23/552 ,  H01L49/02

CPC classification number: H01L27/0682 ,  H01L23/552 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

Abstract translation: 提供了具有由MIM电容器材料形成的电阻结构的集成电路和用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供具有电阻器区域和电容器区域的半导体衬底。 该方法包括在电阻器区域和半导体衬底的电容器区域上沉积电容器材料。 该方法还包括从电阻器区域中的电容器材料形成电阻器结构。 此外，该方法包括在电阻器区域中形成到电阻器结构的电连接。

公开(公告)号：US20150364426A1

公开(公告)日：2015-12-17

申请号：US14303714

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Anurag Mittal ,  Manfred Eller

IPC: H01L23/538 ,  H01L23/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L27/08

CPC classification number: H01L27/0629 ,  H01L27/0805 ,  H01L29/94

Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.

Abstract translation: 本发明的实施例提供了一种改进的去耦电容器结构。 接触区域设置在去耦电容器结构的源极/漏极区域上。 每个接触区域形成为多个段，其中段间间隙将多个段中的段与多个段的相邻段分离。 实施例可以包括两个栅极区域之间的多个接触区域。 去耦电容器的阵列可以被布置为P阱和N阱结构的交替“棋盘”图案，并且可以以与金属化层对角的角度定向，以便于阵列内的多个去耦电容器的连接。

公开(公告)号：US20150228649A1

公开(公告)日：2015-08-13

申请号：US14176660

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/283 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823493 ,  H01L21/845 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/1087 ,  H01L29/6681

Abstract: A fin of a FinFET, being p or n-type, includes a well encompassing the active region, the well being of the opposite type than the fin. An implant of the same type as the well is provided for the well tap at an edge of the active region. A dummy gate material on the fin between the source/drain and the well tap implant reduces an inherent resistance of a well tap contact.

Abstract translation: 具有p型或n型FinFET的鳍包括有源区的阱，与鳍相反的阱的阱。 在活动区域​​的边缘处为井口提供与井相同类型的植入物。 在源极/漏极和阱分接头植入物之间的翅片上的虚拟栅极材料减少了阱分接头的固有电阻。

公开(公告)号：US20150194419A1

公开(公告)日：2015-07-09

申请号：US14148221

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract translation: 三维静电放电（ESD）半导体器件与三维非ESD半导体器件一起制造。 例如，ESD二极管和FinFET制造在相同的体半导体衬底上。 衬底合并技术用于衬底的ESD部分中以形成双宽度鳍片，其上可以使ESD器件更大以处理更多的电流。

公开(公告)号：US10896953B2

公开(公告)日：2021-01-19

申请号：US16382718

申请日：2019-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Shiv Kumar Mishra

IPC: H01L29/06 ,  H01L29/872 ,  H01L27/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US10593754B2

公开(公告)日：2020-03-17

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L21/265 ,  H01L29/06 ,  H01L21/762

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US20200013679A1

公开(公告)日：2020-01-09

申请号：US16030243

申请日：2018-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Edward J. Nowak

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/265

Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

公开(公告)号：US20190245080A1

公开(公告)日：2019-08-08

申请号：US15888195

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

公开(公告)号：US20190088766A1

公开(公告)日：2019-03-21

申请号：US15711410

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial sidewall spacer adjacent a sidewall spacer of a transistor and, with the sacrificial sidewall spacer in position, forming openings in an active layer of an SOI substrate adjacent the sacrificial sidewall spacer so as to thereby expose portions of a buried insulation layer of the SOI substrate. In this example, the method also includes performing an isotropic etching process to form recesses of any shape in the buried insulation layer, wherein the recesses extend laterally under a portion of the active layer, and forming an epi semiconductor material in at least the recesses in the buried insulation layer.