公开(公告)号：US09929290B2

公开(公告)日：2018-03-27

申请号：US15187048

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang ,  Joseph Ervin

IPC: G02B6/12 ,  H01L31/0232 ,  H01L23/48 ,  H01L31/02 ,  G02B6/122 ,  G02B6/42

CPC classification number: H01L31/02327 ,  G02B6/122 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12123 ,  H01L21/76898 ,  H01L23/481 ,  H01L31/02005

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

公开(公告)号：US09711503B2

公开(公告)日：2017-07-18

申请号：US14731569

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L27/085 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

公开(公告)号：US09558999B2

公开(公告)日：2017-01-31

申请号：US14025047

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L21/76885 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76879

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，更具体地涉及一种使用选择性沉积工艺在开口中制造一对超薄金属线的结构和方法。

公开(公告)号：US09557290B2

公开(公告)日：2017-01-31

申请号：US14987329

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

IPC: H01L29/08 ,  G01N27/414 ,  G01N33/487 ,  H01L29/41 ,  H01L21/84 ,  H01L27/12

CPC classification number: G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

Abstract: A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Abstract translation: 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

公开(公告)号：US20150129970A1

公开(公告)日：2015-05-14

申请号：US14079043

申请日：2013-11-13

Applicant: International Business Machine Corporation ,  GlobalFoundries Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/49 ,  H01L27/085

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/092 ,  H01L29/0692 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66628

Abstract: One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon.

Abstract translation: 本文公开的一种方法包括分别在第一和第二间隔开的栅电极结构的每个相对的间隔开的第一和第二端面表面的整个开口中的开口中形成线端保护层，以及 形成邻近每个栅极电极结构的相对侧壁表面的侧壁间隔件，但不邻近具有定位在其上的线端保护层的相对的第一和第二端面表面。

公开(公告)号：US20150054078A1

公开(公告)日：2015-02-26

申请号：US13972348

申请日：2013-08-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin.

Abstract translation: 本文公开的一种方法包括形成堆叠的材料层以形成栅极结构，执行第一蚀刻工艺以通过限定栅极结构的端面的材料层限定开口，在开口中形成栅极分离结构并执行 用于限定栅极结构的侧表面的第二蚀刻工艺。 本文公开的装置包括第一和第二有源区，其包括至少一个鳍状，第一和第二栅极结构，其中每个栅极结构具有端面，以及位于栅极结构之间的栅极分离结构，其中栅极的相对表面 分离结构邻接门结构的​​端面，并且其中门分离结构的上表面位于至少一个翅片的上表面上方。