公开(公告)号：US20190237365A1

公开(公告)日：2019-08-01

申请号：US16379066

申请日：2019-04-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith Kwong Hon Wong ,  Wonwoo Kim ,  Praneet Adusumilli

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/535

Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

公开(公告)号：US10090240B2

公开(公告)日：2018-10-02

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US20180166385A1

公开(公告)日：2018-06-14

申请号：US15893193

申请日：2018-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun Liang ,  Keith Kwong Hon Wong

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76879 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.

公开(公告)号：US09953927B1

公开(公告)日：2018-04-24

申请号：US15497828

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yun-Yu Wang ,  Daniel P. Stambaugh ,  Jeffrey Brown ,  Keith Kwong Hon Wong

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level is formed that includes a conductive feature. A dielectric layer is formed on the metallization level. The dielectric layer includes an opening that extends vertically through the dielectric layer to the conductive feature. An adhesion layer is formed on area of the conductive feature exposed at a base of the opening. The adhesion layer has a thickness equal to a monolayer or a fraction of a monolayer. Another layer (e.g., barrier layer) of a different composition (e.g., TiN) may be deposited on the adhesion layer before the opening is filled with metal deposited by chemical vapor deposition.

公开(公告)号：US20170133278A1

公开(公告)日：2017-05-11

申请号：US15412598

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L27/11 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/8234 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.

公开(公告)号：US09505611B1

公开(公告)日：2016-11-29

申请号：US14814083

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fei Liu ,  Qiqing C. Ouyang ,  Keith Kwong Hon Wong

IPC: B81C1/00 ,  H01L29/66 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/008 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2201/056 ,  B81C2203/0714 ,  H01L27/0617 ,  H01L29/66545

Abstract: Semiconductor devices and methods are provided for integrally forming electromechanical devices (e.g. MEMS or NEMS devices) with CMOS devices in a FEOL (front-end-of-line) structure as part of a replacement metal gate process flow. For example, a method includes forming an electromechanical device in a first device region of a substrate and forming a transistor device in a second device region of the substrate. The electromechanical device includes a sacrificial anchor structure and a sacrificial cantilever structure formed of a sacrificial material. The transistor device includes a sacrificial gate electrode structure formed of the sacrificial material. A replacement metal gate process is performed to replace the sacrificial gate electrode structure of the transistor device with a metallic gate electrode, and to replace the sacrificial anchor structure and the sacrificial cantilever structure with a metallic anchor structure and a metallic cantilever structure. A release process is performed to release the metallic cantilever structure.

Abstract translation: 提供半导体器件和方法，用于在作为替代金属栅极工艺流程的一部分的FEOL（前端线）结构中与CMOS器件一体地形成机电装置（例如MEMS或NEMS器件）。 例如，一种方法包括在衬底的第一器件区域中形成机电器件，并在衬底的第二器件区域中形成晶体管器件。 机电装置包括牺牲锚结构和由牺牲材料形成的牺牲悬臂结构。 晶体管器件包括由牺牲材料形成的牺牲栅电极结构。 执行替换金属栅极处理以用金属栅极电极代替晶体管器件的牺牲栅电极结构，并用金属锚结构和金属悬臂结构代替牺牲锚结构和牺牲悬臂结构。 执行释放过程以释放金属悬臂结构。