公开(公告)号：US11387350B2

公开(公告)日：2022-07-12

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej Pawlak ,  Liesbeth Witters ,  Geoffrey Pourtois

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US20200083116A1

公开(公告)日：2020-03-12

申请号：US16567485

申请日：2019-09-11

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Geert Eneman ,  Vladimir Machkaoutsan

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

公开(公告)号：US20190172913A1

公开(公告)日：2019-06-06

申请号：US16171627

申请日：2018-10-26

Applicant: IMEC VZW

Inventor： Hu Liang ,  Xiuju Zhou ,  Geert Eneman

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L33/32 ,  H01L33/00 ,  H01L29/04 ,  H01L21/02

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

公开(公告)号：US20160027876A1

公开(公告)日：2016-01-28

申请号：US14709696

申请日：2015-05-12

Applicant: IMEC VZW ,  SAMSUNG ELECTRONICS CO. LTD.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L29/10 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract translation: 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US20140151766A1

公开(公告)日：2014-06-05

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US20210336002A1

公开(公告)日：2021-10-28

申请号：US17240694

申请日：2021-04-26

Applicant: IMEC VZW

Inventor： Roger Loo ,  Geert Eneman ,  Clement Porret

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

公开(公告)号：US20200212205A1

公开(公告)日：2020-07-02

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej PAWLAK ,  Liesbeth WITTERS ,  Geoffrey POURTOIS

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US09437681B2

公开(公告)日：2016-09-06

申请号：US14709696

申请日：2015-05-12

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L21/70 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract translation: 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。