公开(公告)号：US11979145B1

公开(公告)日：2024-05-07

申请号：US18064384

申请日：2022-12-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H03K17/687 ,  H02M3/07 ,  H03K3/027 ,  H03K17/693 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K17/6872 ,  H02M3/071 ,  H03K3/027 ,  H03K17/693 ,  H03K19/018521 ,  H03K19/1733 ,  H03K19/20

Abstract: A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.

公开(公告)号：US20240072771A1

公开(公告)日：2024-02-29

申请号：US17898937

申请日：2022-08-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H03K3/012 ,  H03K3/037 ,  H03K5/01

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00013

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

公开(公告)号：US20240046983A1

公开(公告)日：2024-02-08

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  H03K3/356 ,  G11C11/412

CPC classification number: G11C11/419 ,  H03K3/356026 ,  H03K3/356078 ,  G11C11/412

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20240021621A1

公开(公告)日：2024-01-18

申请号：US17812790

申请日：2022-07-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Xuelian Zhu ,  Jia Zeng, JR. ,  Navneet Jain ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

公开(公告)号：US11495288B2

公开(公告)日：2022-11-08

申请号：US17143193

申请日：2021-01-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

IPC: G11C11/419 ,  H01L27/11 ,  G11C11/412

Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

公开(公告)号：US20240282776A1

公开(公告)日：2024-08-22

申请号：US18653473

申请日：2024-05-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

IPC: H01L27/12

CPC classification number: H01L27/1207

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

公开(公告)号：US12050485B2

公开(公告)日：2024-07-30

申请号：US17726171

申请日：2022-04-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

IPC: G06F1/10 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F1/10 ,  G06F15/7839

Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

公开(公告)号：US12046603B2

公开(公告)日：2024-07-23

申请号：US17533402

申请日：2021-11-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

IPC: H01L27/12

CPC classification number: H01L27/1207

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

公开(公告)号：US11929399B2

公开(公告)日：2024-03-12

申请号：US17687941

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/7838

Abstract: Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.

公开(公告)号：US11444031B2

公开(公告)日：2022-09-13

申请号：US17039187

申请日：2020-09-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.