公开(公告)号：US07589379B2

公开(公告)日：2009-09-15

申请号：US10936721

申请日：2004-09-09

申请人： Gehan Anil Joseph Amaratunga ,  Florin Udrea

发明人： Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC分类号： H01L29/72

CPC分类号： H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

摘要： This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication.A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

摘要翻译： 本发明一般涉及诸如功率MOS晶体管，双极晶体管（IGBT）的绝缘栅极，高压二极管等功率半导体及其制造方法。 功率半导体，所述半导体包括：功率器件，所述功率器件具有第一和第二电接触区域和在其间延伸的漂移区域; 以及安装所述装置的半导体衬底; 并且其中所述功率半导体在所述半导体衬底和所述功率器件之间包括电绝缘层，所述电绝缘层具有至少5μm的厚度。

公开(公告)号：US20090008674A1

公开(公告)日：2009-01-08

申请号：US11863231

申请日：2007-09-27

申请人： Florin Udrea

发明人： Florin Udrea

IPC分类号： H01L29/745 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/66348 ,  H01L29/7396

摘要： Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

摘要翻译： 具有两个栅极的双栅极IGBT指的是其中第二栅极用于控制空穴电流的阴极。 在导通状态下，可以大大抑制空穴电流。 在切换期间，允许空穴电流流过第二通道。 结合具有预形成的空穴通道的耗尽型p沟道MOSFET，当0V或者低于特定阈值电压的正电压被施加在第二栅极和阴极之间时，其导通的电压不被用于p沟道栅极的负电压 。 通过增加n阱的掺杂和宽度降低碱运输因子，或者通过减少深阱的掺杂降低注入效率，提供通过积极收集的空穴量的主动控制。 器件至少包括阳极，阴极，半导体衬底，n-漂移区，第一和第二栅极，n +阴极区域; p +阴极短，深p阱，n阱和预形成的孔道。

公开(公告)号：US07465964B2

公开(公告)日：2008-12-16

申请号：US11321051

申请日：2005-12-30

申请人： Florin Udrea

发明人： Florin Udrea

IPC分类号： H01L29/735

CPC分类号： H01L29/7394 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/402

摘要： A high voltage/power semiconductor device has a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. Low and high voltage terminals are connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region and a relatively highly doped injector region between the drift region and the high voltage terminal. The device has a relatively highly doped region in electrical contact with the highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.

摘要翻译： 高电压/功率半导体器件具有衬底，衬底上的绝缘层和绝缘层上的半导体层。 低压端子和高压端子连接到半导体层。 该设备具有控制终端。 半导体层包括位于漂移区和高电压端之间的漂移区和相对高掺杂的注入区。 该器件具有与高度掺杂的注入器区域和高电压端子电接触的相对高掺杂的区域，并与衬底形成半导体结。 绝缘层和第一导电类型的相对高掺杂区域的组合有效地将高度掺杂的注入器区域与衬底隔离。

公开(公告)号：US07301220B2

公开(公告)日：2007-11-27

申请号：US11133445

申请日：2005-05-20

申请人： Florin Udrea

发明人： Florin Udrea

IPC分类号： H01L29/00

CPC分类号： H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

摘要： A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

摘要翻译： 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20070158678A1

公开(公告)日：2007-07-12

申请号：US11321051

申请日：2005-12-30

申请人： Florin Udrea

发明人： Florin Udrea

IPC分类号： H01L29/74

CPC分类号： H01L29/7394 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/402

摘要： A high voltage/power semiconductor device has a relatively lowly doped substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. A low voltage terminal and a high voltage terminal are each electrically connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region of a first conductivity type, the substrate being of the second conductivity type. The semiconductor layer includes a relatively highly doped injector region of the second conductivity type between the drift region and the high voltage terminal, said relatively highly doped injector region being in electrical contact with the high voltage terminal and not being connected via any semiconductor layer to the substrate. The device has a relatively highly doped region of the first conductivity type in electrical contact with the said highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.

摘要翻译： 高电压/功率半导体器件具有相对低掺杂的衬底，衬底上的绝缘层和绝缘层上的半导体层。 低电压端子和高电压端子各自电连接到半导体层。 该设备具有控制终端。 半导体层包括第一导电类型的漂移区，该衬底是第二导电类型。 所述半导体层包括位于所述漂移区和所述高电压端之间的所述第二导电类型的相对高度掺杂的注入区，所述相对高掺杂的注入区与所述高压端子电接触，并且不通过任何半导体层连接到 基质。 该器件具有与所述高掺杂的注入器区域和高电压端子电接触并与衬底形成半导体结的第一导电类型的相对高掺杂的区域。 绝缘层和第一导电类型的相对高掺杂区域的组合有效地将高度掺杂的注入器区域与衬底隔离。

公开(公告)号：US07164154B2

公开(公告)日：2007-01-16

申请号：US10995566

申请日：2004-11-24

申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/15

CPC分类号： H01L29/8083 ,  H01L29/1608

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US20050139859A1

公开(公告)日：2005-06-30

申请号：US10984957

申请日：2004-11-10

申请人： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

发明人： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC分类号： H01L29/80 ,  H01L21/04 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/06

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

摘要： A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

摘要翻译： 碳化硅半导体器件包括衬底和结场效应晶体管。 晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

公开(公告)号：US06900518B2

公开(公告)日：2005-05-31

申请号：US10694735

申请日：2003-10-29

申请人： Florin Udrea ,  Gehan A. J. Amaratunga

发明人： Florin Udrea ,  Gehan A. J. Amaratunga

IPC分类号： H01L21/329 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/20 ,  H01L29/24 ,  H01L29/32 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L29/00 ,  H01L23/58

CPC分类号： H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

摘要翻译： 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US06703684B2

公开(公告)日：2004-03-09

申请号：US09957547

申请日：2001-09-21

申请人： Florin Udrea ,  Gehan A. J. Amaratunga

发明人： Florin Udrea ,  Gehan A. J. Amaratunga

IPC分类号： H01L2900

CPC分类号： H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15,17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

摘要翻译： 功率半导体器件（10）具有包括漂移区（20）的有源区。 漂移区域（20）的至少一部分设置在具有相对的顶表面和底表面（15,17）的膜（16）中。 在一个实施例中，膜（16）的顶表面（15）具有直接或间接连接到其上的电端子，以允许跨越漂移区域（20）横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面（15），并且至少一个电端子直接或间接地连接到底表面（17），以允许垂直地施加电压跨越漂移 区域（20）。 在这些实施例的每一个中，膜（16）的底表面（17）不具有与其相邻定位的半导体衬底。

公开(公告)号：US06566240B2

公开(公告)日：2003-05-20

申请号：US09957609

申请日：2001-09-21

申请人： Florin Udrea ,  Gehan A. J. Amaratunga

发明人： Florin Udrea ,  Gehan A. J. Amaratunga

IPC分类号： H01L2144

CPC分类号： H01L23/3735 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

摘要： A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.