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公开(公告)号：US06995376B2
公开(公告)日：2006-02-07
申请号：US10604204
申请日：2003-07-01
IPC分类号： G01T1/24
CPC分类号： H01L31/1113
摘要： A radiation detector formed using silicon-on-insulator technology. The radiation detector includes a silicon layer formed on an insulating substrate, wherein the silicon layer includes a PNPN structure, and a gate layer formed over the PNPN structure, wherein the gate layer includes a PN gate. Latch-up occurs in the radiation detector only in response to incident radiation.
摘要翻译： 使用绝缘体上硅技术形成的放射线检测器。 放射线检测器包括形成在绝缘基板上的硅层，其中硅层包括PNPN结构，以及形成在PNPN结构上的栅极层，其中栅极层包括PN栅极。 仅在响应入射辐射的情况下，在辐射探测器中发生锁定。
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公开(公告)号：US06794901B2
公开(公告)日：2004-09-21
申请号：US10064921
申请日：2002-08-29
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , Norman J. Rohrer , Peter A. Sandon
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/00338
摘要： An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.
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公开(公告)号：US6097207A
公开(公告)日：2000-08-01
申请号：US138100
申请日：1998-08-21
IPC分类号： H03K19/096 , H03K19/003
CPC分类号： H03K19/0963
摘要： A domino circuit design for handling high stress conditions. The domino logic circuit includes a programmable mechanism for choosing whether the circuit is operating during normal operations or during a stress test, such as a burn-in procedure. In particular, the circuit includes a dual purpose transistor that is controllable by either a precharge signal or an output signal, and includes a mechanism for selecting whether the precharge signal or the output signal is to control the gate input of the dual purpose transistor. Accordingly, the dual purpose transistor will either act in parallel with the precharge device, or a keeper device depending on the mode of operation chosen.
摘要翻译： 用于处理高应力条件的多米诺骨牌电路设计。 多米诺骨牌逻辑电路包括用于选择电路在正常操作期间或在诸如老化过程的压力测试期间操作的可编程机构。 特别地，电路包括可通过预充电信号或输出信号控制的双用途晶体管，并且包括用于选择预充电信号或输出信号是否控制双用晶体管的栅极输入的机构。 因此，双用途晶体管将根据所选择的操作模式与预充电装置或保持器装置并联起作用。
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公开(公告)号：US07715222B2
公开(公告)日：2010-05-11
申请号：US12210712
申请日：2008-09-15
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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25.发明授权Estimating static power consumption of integrated circuits using logic gate templates 失效使用逻辑门模板估算集成电路的静态功耗公开(公告)号：US07681153B2
公开(公告)日：2010-03-16
申请号：US11626020
申请日：2007-01-23
IPC分类号： G06F17/50
CPC分类号： G01R31/2837
摘要： A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output node(s) of the cell. A contribution considers a leakage weight and a leakage probability of a node. A logic template of the cell may be created to better represent a contribution of an internal node to the static power consumption of the cell.
摘要翻译： 公开了一种用于估计集成电路的静态功耗的方法，系统和计算机程序产品。 基于单元的输入节点和输出节点的贡献来表征集成电路的单元的静态功耗。 贡献考虑了节点的泄漏重量和泄漏概率。 可以创建小区的逻辑模板以更好地表示内部节点对小区的静态功耗的贡献。
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公开(公告)号：US20100011278A1
公开(公告)日：2010-01-14
申请号：US12170462
申请日：2008-07-10
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
CPC分类号： H03M13/15 , G06F11/1008 , H03M13/098 , H03M13/13 , H03M13/1505 , H03M13/19
摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.
摘要翻译： 在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位 处理器唤醒时出现软错误，例如作为上电顺序的一部分。
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公开(公告)号：US20090141536A1
公开(公告)日：2009-06-04
申请号：US11947092
申请日：2007-11-29
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US20080037313A1
公开(公告)日：2008-02-14
申请号：US11463917
申请日：2006-08-11
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译： 静态随机存取存储器（SRAM）电路包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。 在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。 在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。
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公开(公告)号：US06969859B2
公开(公告)日：2005-11-29
申请号：US10249872
申请日：2003-05-14
CPC分类号： G01T1/17
摘要： A radiation detecting system including a radiation detecting section having one or more radiation detecting circuits and a circuit adjustment section for adjusting other circuitry to be protected. Radiation detecting circuits are provided to detect a pulse of radiation and/or a total radiation dose accumulation.
摘要翻译： 一种辐射检测系统，包括具有一个或多个辐射检测电路的辐射检测部分和用于调节要被保护的其它电路的电路调整部分。 提供辐射检测电路以检测辐射脉冲和/或总辐射剂量累积。
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公开(公告)号：US06613615B2
公开(公告)日：2003-09-02
申请号：US09976728
申请日：2001-10-12
申请人： Jack A. Mandelman , Fariborz Assaderaghi , Michael J. Hargrove , Peter Smeys , Norman J. Rohrer
发明人： Jack A. Mandelman , Fariborz Assaderaghi , Michael J. Hargrove , Peter Smeys , Norman J. Rohrer
IPC分类号： H01L2100
CPC分类号： H01L27/10897 , H01L21/84 , H01L27/10894 , H01L27/1203 , Y10S257/901 , Y10S257/908
摘要： A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.
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