公开(公告)号：US5753543A

公开(公告)日：1998-05-19

申请号：US624683

申请日：1996-03-25

申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78624 ,  H01L29/78648 ,  Y10S438/91

摘要： A method of forming a bottom gated TFT includes, a) providing a transistor gate relative to a substrate which projects outward thereof; b) providing a dielectric layer over the gate; c) providing a TFT layer of semiconductive material over the dielectric layer; the thin film transistor layer comprising a source area, a channel area, a drain area, and a drain offset area; d) providing a masking layer over the TFT layer; e) anisotropically etching the masking layer to define a masking sidewall spacer laterally adjacent the transistor gate over the drain offset area and leave the channel area outwardly exposed; f) with the masking sidewall spacer in place, implanting a conductivity enhancing impurity of a first type into the thin film channel area to provide a thin film channel region; and g) masking the channel area and the drain offset area while implanting conductivity enhancing impurity of a second type into the thin film source and drain areas to define thin film source and channel regions. Also contemplated is providing a fluorine containing layer over the polycrystalline thin film layer and over the sidewall spacer prior to the channel masking step, followed by annealing thereof at a temperature and for a time which in combination are effective to drive fluorine into the polycrystalline thin film layer and incorporate fluorine within grain boundaries in the polycrystalline thin film to passivate said grain boundaries. Top gated transistors are also contemplated, where the spacer is formed over a substrate elevation step.

公开(公告)号：US20090047776A1

公开(公告)日：2009-02-19

申请号：US12257614

申请日：2008-10-24

申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

IPC分类号： H01L21/28

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。

公开(公告)号：US6017789A

公开(公告)日：2000-01-25

申请号：US881561

申请日：1997-06-24

申请人： Gurtej S. Sandhu ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Pierre C. Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L28/40

摘要： A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta.sub.2 O.sub.5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta.sub.2 O.sub.5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.3, with the sum of "x", "y" and "z" equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.4, where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200.degree. C. to 600.degree. C. and from 0.1 to 100 Torr.

摘要翻译： 形成电介质层的方法包括：a）在衬底顶部化学气相沉积Ta 2 O 5的介电层; 和b）在Ta 2 O 5介电层上方提供主要的无定形扩散阻挡层。 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供第一导电电容器板; c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 以及d）在Ta 2 O 5介电层上提供主要的非晶扩散阻挡层。 还公开了一种电容器结构。 优选的非晶扩散阻挡层是导电的，并且构成金属有机化学气相沉积TiC x N y O z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，“z “在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。 优选通过使用式Ti（NR 2）4的气态钛有机金属前体，其中R选自H和含碳基团，并且使用200℃至600℃的沉积条件来沉积 和0.1至100乇。

公开(公告)号：US5814852A

公开(公告)日：1998-09-29

申请号：US664305

申请日：1996-06-11

申请人： Gurtej S. Sandhu ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Pierre C. Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/62

CPC分类号： H01L28/56 ,  H01L28/40

摘要： A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta.sub.2 O.sub.5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta.sub.2 O.sub.5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta.sub.2 O.sub.5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.3, with the sum of "x", "y" and "z" equalling about 1.0. Such is preferably deposited by utilizing a gaseous titanium organometallic precursor of the formula Ti(NR.sub.2).sub.4, where R is selected from the group consisting of H and a carbon containing radical, and utilizing deposition conditions of from 200.degree. C. to 600.degree. C. and from 0.1 to 100 Torr.

摘要翻译： 形成电介质层的方法包括：a）在衬底顶部化学气相沉积Ta 2 O 5的介电层; 和b）在Ta 2 O 5介电层上方提供主要的无定形扩散阻挡层。 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供第一导电电容器板; c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 以及d）在Ta 2 O 5介电层上提供主要的非晶扩散阻挡层。 还公开了一种电容器结构。 优选的非晶扩散阻挡层是导电的，并且构成金属有机化学气相沉积TiC x N y O z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，“z “在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。 优选通过使用式Ti（NR 2）4的气态钛有机金属前体，其中R选自H和含碳基团，并且使用200℃至600℃的沉积条件来沉积 和0.1至100乇。

公开(公告)号：US5392189A

公开(公告)日：1995-02-21

申请号：US104524

申请日：1993-08-10

申请人： Pierre C. Fazan ,  Gurtej S. Sandhu

发明人： Pierre C. Fazan ,  Gurtej S. Sandhu

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01G1/01

CPC分类号： H01L27/11502 ,  H01L21/76849 ,  H01L21/7687 ,  H01L21/76889 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/60 ,  H01L27/10855 ,  H01L28/55 ,  H01L28/75

摘要： The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.

公开(公告)号：US6087700A

公开(公告)日：2000-07-11

申请号：US21729

申请日：1998-02-11

申请人： Pierre C. Fazan ,  Hiang C. Chan

发明人： Pierre C. Fazan ,  Hiang C. Chan

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/76

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061

摘要： A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

摘要翻译： 制造具有硅化钛阻挡层的栅极的方法包括形成栅氧化层的步骤。 栅极氧化物可以使用标准LOCOS工艺形成。 掺杂多晶硅层沉积在栅极氧化物层上。 相对于掺杂多晶硅层以预定的关系形成硅化钛层，即其可沉积在多晶硅的顶部或形成在多晶硅层的顶表面中。 在硅化钛层的顶部上沉积一层硅化钨。 蚀刻栅极氧化物，掺杂多晶硅，硅化钛和硅化钨的层以形成栅极。 还公开了如此制造的栅极。

公开(公告)号：US5798296A

公开(公告)日：1998-08-25

申请号：US649803

申请日：1996-05-17

申请人： Pierre C. Fazan ,  Hiang C. Chan

发明人： Pierre C. Fazan ,  Hiang C. Chan

IPC分类号： H01L21/28 ,  H01L29/49

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061

摘要： A method of fabricating a gate having a barrier layer of titanium silicide is comprised of the steps of forming a layer of gate oxide. The gate oxide may be formed using a standard LOCOS process. A layer of doped polysilicon is deposited over the layer of gate oxide. A layer of titanium silicide is formed in a predetermined relationship with respect the layer of doped polysilicon, i.e., it may be deposited on top of the polysilicon or formed in a top surface of the polysilicon layer. A layer of tungsten silicide is deposited on top of the layer of titanium silicide. The layers of gate oxide, doped polysilicon, titanium silicide, and tungsten silicide are etched to form the gate. A gate thus fabricated is also disclosed.

公开(公告)号：US5313087A

公开(公告)日：1994-05-17

申请号：US129872

申请日：1993-09-30

申请人： Hiang C. Chan ,  Pierre C. Fazan ,  Bohr-Winn Shih

发明人： Hiang C. Chan ,  Pierre C. Fazan ,  Bohr-Winn Shih

IPC分类号： H01L21/02 ,  H01L21/3215 ,  H01L21/265 ,  G11C11/00 ,  G11C11/36 ,  H01L29/04

CPC分类号： H01L28/20 ,  H01L21/32155

摘要： A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.

摘要翻译： 多晶硅层设置有p型杂质，并用氧化物掩模掩蔽以限定多晶硅层的p型区域。 然后将第二杂质提供到多晶硅层的第一未掩模区域中。 沉积第二氧化物掩模并各向异性蚀刻以形成与第一氧化物掩模相邻的间隔物。 间隔物限定与p型区域相邻的多晶硅层的两个扩散阻挡区域。 然后将n型杂质提供到多晶硅层的第二未掩模区域中以形成与扩散阻挡区域相邻的两个n型区域。 扩散阻挡区域防止p型和n型杂质在多晶硅层内的交叉扩散，同时也具有足够的尺寸以允许正常的p / n操作。

公开(公告)号：US20090302322A1

公开(公告)日：2009-12-10

申请号：US12492991

申请日：2009-06-26

申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

IPC分类号： H01L29/786 ,  H01L21/20

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

公开(公告)号：US07566907B2

公开(公告)日：2009-07-28

申请号：US12135761

申请日：2008-06-09

申请人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

发明人： Gurtej S. Sandhu ,  Shubneesh Batra ,  Pierre C. Fazan

IPC分类号： H01L21/00

CPC分类号： H01L29/78678 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78672 ,  H01L29/78675

摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。