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    Memory Monitoring Method and Related Apparatus
    21.
    发明申请
    Memory Monitoring Method and Related Apparatus 有权
    内存监控方法及相关设备

    公开(公告)号：US20150301917A1

    公开(公告)日：2015-10-22

    申请号：US14754011

    申请日：2015-06-29

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zehan Cui ,  Mingyu Chen ,  Licheng Chen ,  Mingyang Chen

    IPC: G06F11/30 ,  G06F13/16

    CPC classification number: G06F11/3037 ,  G06F11/3027 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/10 ,  G06F12/12 ,  G06F13/1663 ,  G06F2201/815 ,  G06F2201/88

    Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

    Abstract translation: 内存监控方法和计算系统。 计算系统包括处理器，存储器和监视器。 监视器获取计算机系统的存储单元访问信息和处理信息。 存储器单元访问信息包括存储器的每个存储器单元的访问次数。 处理信息包括关于由当前运行进程访问的每个存储器单元的虚拟地址和物理地址之间的映射关系的信息。 在产生包括当前运行进程访问每个存储单元的频率的监视信息之后，根据存储器单元访问信息和处理信息，监视器将监视信息反馈给处理器。 因此，处理器可以根据监视信息执行存储器管理。

    Method for accessing extended memory, device, and system
    22.
    发明授权
    Method for accessing extended memory, device, and system 有权

    公开(公告)号：US10545672B2

    公开(公告)日：2020-01-28

    申请号：US15788990

    申请日：2017-10-20

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

    IPC: G06F3/06

    Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

    METHOD FOR ACCESSING EXTENDED MEMORY, DEVICE, AND SYSTEM
    24.
    发明申请
    METHOD FOR ACCESSING EXTENDED MEMORY, DEVICE, AND SYSTEM 审中-公开

    公开(公告)号：US20180039424A1

    公开(公告)日：2018-02-08

    申请号：US15788990

    申请日：2017-10-20

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

    Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

    IPC: G06F3/06

    Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

    Message-based memory access apparatus and access method thereof
    25.
    发明授权
    Message-based memory access apparatus and access method thereof 有权

    公开(公告)号：US09870327B2

    公开(公告)日：2018-01-16

    申请号：US14335029

    申请日：2014-07-18

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/1673 ,  G06F13/4239

    Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

    Reducing latency in an expanded memory system
    27.
    发明授权
    Reducing latency in an expanded memory system 有权

    公开(公告)号：US09812186B2

    公开(公告)日：2017-11-07

    申请号：US14922973

    申请日：2015-10-26

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Yuan Ruan ,  Mingyu Chen

    IPC: G11C11/406 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

    CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

    Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.

    DATA OPERATING METHOD, DEVICE, AND SYSTEM
    28.
    发明申请
    DATA OPERATING METHOD, DEVICE, AND SYSTEM 审中-公开
    数据操作方法，设备和系统

    公开(公告)号：US20170068452A1

    公开(公告)日：2017-03-09

    申请号：US15357408

    申请日：2016-11-21

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Fei Xia ,  Mingyu Chen ,  Dejun Jiang ,  Jin Xiong

    IPC: G06F3/06 ,  G06F12/0868

    CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0676 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/312 ,  G06F2212/461

    Abstract: A data operating method, device, and system are provided. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.

    Abstract translation: 提供数据操作方法，设备和系统。 该方法包括：接收CPU发送的操作指令; 当操作指令是读取指令时，读取块装置中的第一数据块并将第一数据块中的读取数据返回给CPU; 或者当操作指令是写入指令时，将写入指令所指示的写入数据写入高速缓存，并向块装置写入包括待写入数据的第二数据块。 该方法用于在块设备中操作数据。

    Address compression method, address decompression method, compressor, and decompressor
    30.
    发明授权
    Address compression method, address decompression method, compressor, and decompressor 有权
    地址压缩方法，地址解压缩方法，压缩器和解压缩器

    公开(公告)号：US09495304B2

    公开(公告)日：2016-11-15

    申请号：US14687607

    申请日：2015-04-15

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Yuan Ruan

    IPC: G06F12/00 ,  G06F12/10 ,  G06F9/30 ,  G06F9/35 ,  G06F13/38 ,  G06F17/30

    CPC classification number: H03M7/6011 ,  G06F9/30138 ,  G06F9/35 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/385 ,  G06F17/30153 ,  G06F2212/6032 ,  G06F2212/657

    Abstract: An address compression method, an address decompression method, a compressor, and a decompressor are disclosed, wherein the address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

    Abstract translation: 公开了一种地址压缩方法，地址解压缩方法，压缩器和解压缩器，其中地址压缩方法包括在压缩器接收到由第一处理器发送的多个操作请求消息之后，根据由 在具有相同流号的所有操作请求消息中携带的地址信息，与具有相同流号的操作请求消息相对应的压缩算法; 然后根据确定的压缩算法压缩具有相同流号的操作请求消息中承载的地址。 本发明可应用于计算机领域。

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