公开(公告)号：US20080308860A1

公开(公告)日：2008-12-18

申请号：US12213305

申请日：2008-06-18

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Suk-Kang Sung ,  Se-Jun Park

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Suk-Kang Sung ,  Se-Jun Park

IPC分类号： H01L27/11 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11529 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.

摘要翻译： 提供一种形成半导体器件图案的方法，形成电荷存储图案的方法，包括电荷存储图案的非易失性存储器件及其制造方法。 形成电荷存储图案的方法包括在衬底上形成沟槽，以及在沟槽中形成器件隔离图案。 器件隔离图案从衬底的表面突出出来，形成露出衬底的开口。 在开口中的基板上形成隧道氧化物层。 通过导电材料的选择性沉积，在隧道氧化物层和器件隔离图案上形成初步电荷存储图案。 初步电荷存储图案可以从器件隔离图案中去除。 初始电荷存储图案仅保留在隧道氧化物层上，以在基板上形成电荷存储图案。

公开(公告)号：US20050255643A1

公开(公告)日：2005-11-17

申请号：US11112818

申请日：2005-04-21

申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/66818

摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.

摘要翻译： 提供了一种使用镶嵌工艺形成鳍式晶体管的方法。 填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。 图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。 形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。 通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

公开(公告)号：US20050167754A1

公开(公告)日：2005-08-04

申请号：US11046722

申请日：2005-02-01

申请人： Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

发明人： Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L29/66818 ,  Y10S257/90

摘要： A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.

摘要翻译： 公开了一种翅片式MOSFET及其制造方法。 鳍型MOSFET中的栅极结构通过未经光刻工艺的镶嵌工艺形成。 用于形成沟道区域的杂质被选择性地注入到与栅极结构相邻的半导体衬底的部分中。

公开(公告)号：US08217467B2

公开(公告)日：2012-07-10

申请号：US12984860

申请日：2011-01-05

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

摘要翻译： 在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。 半导体存储器件还包括在衬底上的器件隔离图案。 器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。 半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。 半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。 半导体存储器件还包括第三有源区中的第三源/漏区。 半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

公开(公告)号：US08053347B2

公开(公告)日：2011-11-08

申请号：US12379190

申请日：2009-02-13

申请人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： H01L21/3205

CPC分类号： H01L21/28052 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成多个栅极结构，所述栅极结构各自包括堆叠在栅极导电图案上的硬掩模图案，在栅极结构之间形成至少部分地暴露顶部的绝缘层图案 形成通过选择性地去除硬掩模图案而暴露出栅极导电图案的至少顶表面的沟槽，以及在暴露的栅极导电图案上形成硅化物层的沟槽。

公开(公告)号：US20110170356A1

公开(公告)日：2011-07-14

申请号：US13072022

申请日：2011-03-25

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： G11C16/26

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/11524

摘要： Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

摘要翻译： 提供了在非易失性存储单元中编程数据的方法。 根据一些实施例的存储器单元可以包括栅极结构，其包括隧道氧化物层图案，浮动栅极，电介质层和顺序堆叠在衬底上的控制栅极，杂质区域形成在衬底的两侧的衬底中 栅极结构以及与浮动栅极间隔开并面对浮栅的导电层图案。 这种方法的实施例可以包括将编程电压施加到控制栅极，使杂质区域接地并且向导电层图案施加边缘电压以在浮动栅极中产生边缘场。

公开(公告)号：US07911847B2

公开(公告)日：2011-03-22

申请号：US12289847

申请日：2008-11-05

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

摘要： A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit data into second cells coupled to the other of the at least one even bitline and the at least one odd bitline, where N is a natural number greater than one and M is a natural number greater than N.

摘要翻译： 一种在包括至少一个偶数位线和至少一个奇数位线的NAND闪存器件中编程数据的方法，所述方法包括将N位数据编程到耦合到所述至少一个偶数位线或所述至少一个奇数位线 以及将M位数据编程到耦合到所述至少一个偶数位线和所述至少一个奇数位线中的另一个的第二单元中，其中N是大于1的自然数，M是大于N的自然数。

公开(公告)号：US07868467B2

公开(公告)日：2011-01-11

申请号：US12167875

申请日：2008-07-03

申请人： Choong-Ho Lee ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Choong-Ho Lee ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L29/40

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L24/32 ,  H01L24/83 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7781 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/792 ,  H01L2224/2919 ,  H01L2224/838 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0665 ,  H01L2924/00

摘要： A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

摘要翻译： 半导体器件包括第一衬底，多个单元晶体管和第二衬底。 第一基板具有与第一表面相对的第一表面和第二表面。 多个单元晶体管形成在第一基板的第一表面上沿一个方向延伸。 第二基板具有与第一基板的第二表面接触的上表面。 此外，第二基板的上表面具有弯曲结构，以在多个单元晶体管的延伸方向上向第一基板施加拉伸应力。 因此，可以向第一衬底施加拉伸应力以改善电池晶体管的沟道区域中载流子的迁移率。

公开(公告)号：US20090166714A1

公开(公告)日：2009-07-02

申请号：US12318451

申请日：2008-12-30

申请人： Suk-Kang Sung ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

发明人： Suk-Kang Sung ,  Choong-Ho Lee ,  Dong-Uk Choi ,  Hee-Soo Kang

IPC分类号： H01L29/792

CPC分类号： H01L27/11568

摘要： A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

摘要翻译： 非易失性存储器件包括在衬底上的场绝缘层图案，以限定衬底的有源区，场绝缘层图案的上部突出在衬底的上表面上，在有源区上的隧道绝缘层， 隧道绝缘层上的电荷俘获层，电荷俘获层上的阻挡层，场绝缘层图案的上表面上的第一绝缘层，以及阻挡层和第一绝缘层上的字线结构。

公开(公告)号：US07358142B2

公开(公告)日：2008-04-15

申请号：US11046623

申请日：2005-01-28

申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源区和漏区形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。