公开(公告)号：US08669608B2

公开(公告)日：2014-03-11

申请号：US13419984

申请日：2012-03-14

申请人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

发明人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/265 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66833

摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

摘要翻译： 根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括： 形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

公开(公告)号：US20120235221A1

公开(公告)日：2012-09-20

申请号：US13236723

申请日：2011-09-20

申请人： Megumi ISHIDUKI ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

发明人： Megumi ISHIDUKI ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L21/425 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

摘要翻译： 根据一个实施例，半导体器件包括衬底，第一层叠体，存储膜，第一通道体，第二堆叠体，栅极绝缘膜和第二通道体。 在选择栅极的侧面和第二绝缘层之间形成台阶部。 覆盖第二通道体的台阶部分的部分的膜厚比设置在第二通道体的第二绝缘层之间的部分的膜厚度厚。

公开(公告)号：US08581329B2

公开(公告)日：2013-11-12

申请号：US13236723

申请日：2011-09-20

申请人： Megumi Ishiduki ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

发明人： Megumi Ishiduki ,  Ryota Katsumata ,  Tomo Ohsawa ,  Mitsuru Sato ,  Masaru Kidoh ,  Hiroyasu Tanaka

IPC分类号： H01L29/792 ,  H01L21/425

CPC分类号： H01L21/425 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.

摘要翻译： 根据一个实施例，半导体器件包括衬底，第一层叠体，存储膜，第一通道体，第二堆叠体，栅极绝缘膜和第二通道体。 在选择栅极的侧面和第二绝缘层之间形成台阶部。 覆盖第二通道体的台阶部分的部分的膜厚比设置在第二通道体的第二绝缘层之间的部分的膜厚度厚。

公开(公告)号：US09076820B2

公开(公告)日：2015-07-07

申请号：US13600373

申请日：2012-08-31

申请人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

发明人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

公开(公告)号：US06924523B2

公开(公告)日：2005-08-02

申请号：US10391889

申请日：2003-03-19

申请人： Hideaki Aochi ,  Mitsuru Sato ,  Eiji Yoshida

发明人： Hideaki Aochi ,  Mitsuru Sato ,  Eiji Yoshida

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L27/108

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L28/91

摘要： A semiconductor memory device includes a semiconductor substrate and a support layer provided above the semiconductor substrate. Particles are formed on the support layer. A first electrode is provided on the support layer such that it covers the particles. The first electrode has a first interface located opposite to the particles and being wavy in accordance with the pattern of the particles. A capacitor insulation film is provided on the first interface. The capacitor insulation film has a second interface located opposite to the first interface and being wavy in accordance with the shape of the first interface. A second electrode is provided on the capacitor insulation film.

摘要翻译： 半导体存储器件包括半导体衬底和设置在半导体衬底之上的支撑层。 颗粒形成在支撑层上。 第一电极设置在支撑层上，使得其覆盖颗粒。 第一电极具有与颗粒相对的第一界面，并且根据颗粒的图案是波浪形的。 在第一接口上设置电容绝缘膜。 电容绝缘膜具有与第一界面相对的第二界面，并且根据第一界面的形状为波状。 在电容绝缘膜上设置第二电极。

公开(公告)号：US20080219054A1

公开(公告)日：2008-09-11

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US07091546B2

公开(公告)日：2006-08-15

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L29/772

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US20080017992A1

公开(公告)日：2008-01-24

申请号：US11826224

申请日：2007-07-13

申请人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

发明人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

IPC分类号： H01L21/311 ,  H01L23/48

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/105 ,  H01L27/1052

摘要： A first hard mask is formed on a polysilicon film or a target member to be etched, on which a second hard mask composed of amorphous silicon is formed. Ions of boron or the like are implanted into a desired portion of the second hard mask, and then the first hard mask is etched with a mask of the second hard mask. Only the portion not ion-implanted of the second hard mask is etched off by wet etching. A sidewall film is formed on sidewalls of the first hard mask, and then the first hard mask having an upper portion exposed, not covered with the second hard mask is selectively etched off.

摘要翻译： 第一硬掩模形成在多晶硅膜或要蚀刻的靶构件上，在其上形成由非晶硅构成的第二硬掩模。 将硼等的离子注入到第二硬掩模的期望部分中，然后用第二硬掩模的掩模蚀刻第一硬掩模。 通过湿式蚀刻仅蚀刻第二硬掩模未离子注入的部分。 在第一硬掩模的侧壁上形成侧壁膜，然后选择性地蚀刻除去未被第二硬掩模覆盖的具有暴露的上部的第一硬掩模。

公开(公告)号：US07813203B2

公开(公告)日：2010-10-12

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C7/02

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US20050184323A1

公开(公告)日：2005-08-25

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor adjacently formed to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，与沟槽电容器相邻形成并具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域的单元晶体管， 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区域之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。