公开(公告)号：US20060236132A1

公开(公告)日：2006-10-19

申请号：US11106493

申请日：2005-04-15

申请人： Hung-Ming Chen ,  Bor-Tay Chen

发明人： Hung-Ming Chen ,  Bor-Tay Chen

IPC分类号： G06F1/26

CPC分类号： G06F1/3215

摘要： A power-managing key apparatus uses a power key to integrate the function of ACPI management of computer hardware and hibernation on/off of operation system. A processor coupled to the power key detects pressing-time parameters of the power key and a current state of the computer. The processor sends a hardware signal to emulate ACPI power button function in order to power on/off computer and awake the computer from a power saving mode. The processor sends a software signal to an operation system of the computer to disable/enable a hibernation state. Therefore, the complicated power management performed by computer hardware and operation system can be simplified.

摘要翻译： 电源管理密钥设备使用电源密钥来整合计算机硬件的ACPI管理功能和操作系统的休眠模式。 耦合到电源键的处理器检测电源键的按压时间参数和计算机的当前状态。 处理器发送硬件信号以模拟ACPI电源按钮功能，以便打开/关闭计算机，并从计算机唤醒电脑。 处理器将软件信号发送到计算机的操作系统以禁用/启用休眠状态。 因此，可以简化由计算机硬件和操作系统执行的复杂功率管理。

公开(公告)号：US07104842B1

公开(公告)日：2006-09-12

申请号：US11315497

申请日：2005-12-23

申请人： Ching-Hsiung Huang ,  Hung-Ming Chen

发明人： Ching-Hsiung Huang ,  Hung-Ming Chen

IPC分类号： H01R13/648 ,  H01R13/625

CPC分类号： H01R13/6594 ,  H01R13/6582

摘要： An electromagnetic interference diminishing structure of a connector assembly. The connector assembly includes a socket and a plug. The socket includes a main body enclosed by a metal housing connected to the grounding circuit of a circuit board. The plug includes a shield metal housing formed with grounding sections. A terminal main body is inserted in the shield metal housing. An insulating housing is fitted around the shield metal housing. When a front section of the plug is plugged into the socket, the metal housing of the socket and the grounding sections of the shield metal housing of the plug contact with each other through the holes of the insulating housing of the plug. Accordingly, the electromagnetic interference can be effectively diminished.

摘要翻译： 连接器组件的电磁干扰减小的结构。 连接器组件包括插座和插头。 插座包括由与电路板的接地电路连接的金属外壳包围的主体。 插头包括形成有接地部分的屏蔽金属壳体。 端子主体插入屏蔽金属外壳中。 绝缘壳体安装在屏蔽金属外壳周围。 当插头的前部插入插座时，插座的金属外壳和插头的屏蔽金属外壳的接地部分通过插头的绝缘外壳的孔相互接触。 因此，可以有效地减少电磁干扰。

公开(公告)号：US20050032354A1

公开(公告)日：2005-02-10

申请号：US10634086

申请日：2003-08-04

申请人： Yin-Shen Chu ,  Hung-Ming Chen

发明人： Yin-Shen Chu ,  Hung-Ming Chen

IPC分类号： H01L21/311 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method for selectively etching a semiconductor feature opening to controllably achieve a critical dimension accuracy including providing a semiconductor wafer including a first opening formed extending through a thickness of at least one dielectric insulating layer and having an uppermost inorganic BARC layer; depositing a photoresist layer over the uppermost BARC layer and patterning the photoresist layer to form an etching pattern for etching a second opening overlying and encompassing the first opening; carrying out a first plasma assisted etching process to etch through a thickness of the BARC layer including a predetermined amount of CO in a plasma etching chemistry to increase an etching resistance of the photoresist layer; and, carrying out a second plasma assisted etching process to etch through a thickness portion of the at least one dielectric insulating layer to form the second opening.

公开(公告)号：US08592918B2

公开(公告)日：2013-11-26

申请号：US12843658

申请日：2010-07-26

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L21/02

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211

摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

摘要翻译： 集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。 两个绝缘区域包括具有第一k值的第一电介质材料。 半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。 另外的绝缘区域位于第二器件区域和衬底之上。 附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

公开(公告)号：US08519481B2

公开(公告)日：2013-08-27

申请号：US12612442

申请日：2009-11-04

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L27/088

CPC分类号： H01L27/0203 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

摘要翻译： 集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并相邻的第一半导体条带。 第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

公开(公告)号：US08482073B2

公开(公告)日：2013-07-09

申请号：US12731411

申请日：2010-03-25

申请人： Hung-Ming Chen ,  Shao-Ming Yu ,  Chang-Yun Chang

发明人： Hung-Ming Chen ,  Shao-Ming Yu ,  Chang-Yun Chang

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/772

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/7848 ,  H01L29/785

摘要： An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.

摘要翻译： 提供了包括多个Fin场效应晶体管（FINFET）的集成电路。 集成电路包括在衬底上的多个鳍状通道体。 鳍状通道体包括第一鳍状物通道体和第二鳍状物通道体。 栅极结构设置在翅片通道体上。 第一FINFET的至少一个第一源极/漏极（S / D）区域与第一鳍片通道主体相邻。 第二FINFET的至少一个第二源极/漏极（S / D）区域与第二鳍片通道主体相邻。 所述至少一个第一S / D区域与所述至少一个第二S / D区域电耦合。 至少一个第一和第二S / D区域基本上不包括任何翅片结构。

公开(公告)号：US20130062669A1

公开(公告)日：2013-03-14

申请号：US13227979

申请日：2011-09-08

申请人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

发明人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  B82Y40/00

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

摘要： Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.

公开(公告)号：US08264542B2

公开(公告)日：2012-09-11

申请号：US12204163

申请日：2008-09-04

申请人： Kual-Zheng Lee ,  Fan-Di Jou ,  Hung-Ming Chen

发明人： Kual-Zheng Lee ,  Fan-Di Jou ,  Hung-Ming Chen

IPC分类号： H04N7/18

CPC分类号： G06K9/3233 ,  G06T7/292 ,  G06T2207/10016 ,  G06T2207/30236

摘要： A system for image processing is provided. The system includes a region of interest (ROI) module receiving video from a camera and detects a ROI(s) in a first image. A lookup table generates a value responsive to block type for a first vanishing point (VP). A labeling module identifies a point “p” most close to the first VP, a point “q” most remote to the first VP and a length “h” between “p” and “q” in each ROI(s), and generates information on p, q and h. Another lookup table generates information on p′, q′ and h′, wherein p′ is a point most close to a second VP, q′ is a point most remote to the second VP and h′ is a length between p′ and q′ in ROI(s) in the second image. A transforming module transforms ROI(s) in the first image into an ROI in the second image.

摘要翻译： 提供了一种用于图像处理的系统。 该系统包括感兴趣区域（ROI）模块，其从相机接收视频并检测第一图像中的ROI。 查找表根据第一个消失点（VP）的块类型生成一个值。 标签模块识别最接近第一VP的点“p”，最远离第一VP的点“q”和每个ROI中的“p”和“q”之间的长度“h”，并且生成 关于p，q和h的信息。 另一个查找表生成关于p'，q'和h'的信息，其中p'是最靠近第二VP的点，q'是最靠近第二VP的点，h'是p'和q之间的长度 “在第二张图像中的ROI中。 变换模块将第一图像中的ROI转换为第二图像中的ROI。

公开(公告)号：US08008157B2

公开(公告)日：2011-08-30

申请号：US11588920

申请日：2006-10-27

申请人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.

摘要翻译： 形成半导体结构的方法包括形成PMOS器件和NMOS器件。 形成PMOS器件的步骤包括在半导体衬底上形成第一栅叠层; 在所述第一栅极堆叠的侧壁上形成第一偏移间隔物; 使用第一偏移间隔件作为掩模在半导体衬底中形成应力器; 并且在应激源上外延生长第一升高的源极/漏极延伸（LDD）区域。 形成NMOS器件的步骤包括在半导体衬底上形成第二栅极叠层; 在所述第二栅极堆叠的侧壁上形成第二偏移间隔物; 使用第二偏移间隔物作为掩模在半导体衬底上外延生长第二隆起的LDD区; 以及形成与第二凸起LDD区域相邻的深源极/漏极区域。

公开(公告)号：US20110095372A1

公开(公告)日：2011-04-28

申请号：US12843658

申请日：2010-07-26

申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L27/088

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211

摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

摘要翻译： 集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。 两个绝缘区域包括具有第一k值的第一电介质材料。 半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。 另外的绝缘区域位于第二器件区域和衬底之上。 附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。