公开(公告)号：US09449671B2

公开(公告)日：2016-09-20

申请号：US14132987

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC: G11C7/02 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C7/02 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Abstract translation: 公开了用于概率动态随机存取存储器（DRAM）行修复的示例。 在一些示例中，使用DRAM的行敲击限制和DRAM的最大激活率可以确定概率行锤检测值。 然后可以使用概率行锤检测值，使得概率可接受地低，以致对DRAM的侵入行进行的给定激活导致在对一个或多个受害行进行相关联的调度行刷新之前超过行敲击限制 与侵略者行。 其他的例子被描述和要求保护。

公开(公告)号：US20160179610A1

公开(公告)日：2016-06-23

申请号：US14578413

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/08 ,  G06F11/16

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Abstract translation: 数据通过链路从内存缓冲设备发送到主机设备。 确定数据中的错误。 读取响应消除信号被发送到主机设备以向主机设备指示错误，其中在将数据从存储器缓冲器件发送到主机设备之后要发送读取响应消除信号。

公开(公告)号：US20240160585A1

公开(公告)日：2024-05-16

申请号：US18419159

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F12/14 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/00

Abstract: A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

公开(公告)号：US20240012759A1

公开(公告)日：2024-01-11

申请号：US18462561

申请日：2023-09-07

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F13/1673 ,  G06F13/4282 ,  G06F12/0806 ,  G06F12/0808 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/1016

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US20210240623A1

公开(公告)日：2021-08-05

申请号：US17236692

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US10579464B2

公开(公告)日：2020-03-03

申请号：US15912450

申请日：2018-03-05

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US10061719B2

公开(公告)日：2018-08-28

申请号：US14583147

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C5/04

CPC classification number: G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

公开(公告)号：US10031861B2

公开(公告)日：2018-07-24

申请号：US14865304

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Binata Bhattacharyya ,  Raghunandan Makaram ,  Brian S. Morris

IPC: G06F12/14 ,  G06F12/0802 ,  H04L9/30 ,  H04L9/32 ,  H04L9/06

Abstract: A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in an off-chip memory. A memory encryption engine (MEE) may be operatively coupled to the memory controller and the off-chip memory. The MEE may store non-MEE metadata bits within a modified version line corresponding to ones of a plurality of data lines stored in a protected region of the off-chip memory, compute an embedded message authentication code (eMAC) using the modified version line, and detect an attempt to modify one of the non-MEE metadata bits by using the eMAC within a MEE tree walk to authenticate access to the plurality of data lines. The non-MEE metadata bits may store coherence bits that track changes to a cache line in a remote socket, poison bits that track error containment within the data lines, and possibly other metadata bits.

公开(公告)号：US20170322841A1

公开(公告)日：2017-11-09

申请号：US15462185

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/08 ,  H04L1/00 ,  G06F13/00 ,  G06F11/16 ,  H04L1/18

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US20170185315A1

公开(公告)日：2017-06-29

申请号：US14757926

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.