公开(公告)号：US20220393960A1

公开(公告)日：2022-12-08

申请号：US17846947

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Peter McCarthy ,  Chris MacNamara ,  John Browne ,  Liang J. Ma ,  Liam Day

IPC: H04L43/10 ,  H04L41/0833 ,  H04L43/022 ,  H04L43/16 ,  G06F1/3209

Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

公开(公告)号：US11451470B2

公开(公告)日：2022-09-20

申请号：US16755554

申请日：2016-08-05

Applicant: Intel Corporation

Inventor： Damien Power ,  Chris MacNamara ,  Marco Varlese

IPC: H04L12/725 ,  H04L12/24 ,  H04L12/46 ,  H04L29/08 ,  H04L29/12 ,  H04L29/06 ,  H04L45/302 ,  H04L41/0806 ,  H04L41/0893 ,  H04L41/0896 ,  H04L69/16 ,  H04L61/5007 ,  H04L67/63

Abstract: A Service Routing Agent and methods are disclosed that classify and route data service requests. One embodiment includes a control circuit and at least one orchestrator, processor, and service handler circuit. The control circuit performs a process to: receive a configuration of at least one service handler circuit, initialize a list of service handler circuits and associated applications, program the at least one processor to listen for data service requests associated with the application, receive a data service request, and determine whether a service handler circuit associated with the application has been activated; when the service handler circuit has been activated, forwards the data service request to the service handler circuit, and when the service handler circuit has not been activated, request that the service handler circuit be activated, and then forwards the data service request to the service handler circuit. The Service Routing Agent reports updated traffic statistics.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US10966135B2

公开(公告)日：2021-03-30

申请号：US16147220

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Jonas Svennebring ,  Niall D. McDonnell ,  Andrey Chilikin ,  Andrew Cunningham ,  Chris MacNamara ,  Carl-Oscar Montelius ,  Eliezer Tamir ,  Bjorn Topel

IPC: H04W36/30 ,  H04W36/36 ,  H04L12/715 ,  H04W76/27 ,  H04L12/717 ,  H04W36/32 ,  H04W40/18 ,  H04W36/00 ,  H04W24/10 ,  H04L12/741

Abstract: Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

公开(公告)号：US10341264B2

公开(公告)日：2019-07-02

申请号：US15199110

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris MacNamara ,  Pierre Laurent ,  Sean Harte

IPC: H04L12/879 ,  H04L12/43 ,  H04L12/927 ,  H04L12/935 ,  H04L12/861

Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.

公开(公告)号：US10331590B2

公开(公告)日：2019-06-25

申请号：US15198714

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Chris MacNamara ,  Tomasz Kantecki ,  John J. Browne

IPC: G06F13/10 ,  G06F13/28 ,  G06T1/20

Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described.

公开(公告)号：US10200410B2

公开(公告)日：2019-02-05

申请号：US15282564

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Michael Hingston McLaughlin Bursell ,  Stephen T. Palermo ,  Chris MacNamara ,  Pierre Laurent ,  John J. Browne

IPC: H04L29/06

Abstract: A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust assessment ruleset to determine whether the system security controller is trusted/trustworthy. An untrusted system security controller peer device is replaced by another of the peer devices selected by the peer devices. The current system security controller peer device transfers system threat information and security risk information collected from the peer devices to the new system security controller elected by the peer devices.

公开(公告)号：US20230412459A1

公开(公告)日：2023-12-21

申请号：US18241609

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Ciara Loftus ,  Chris MacNamara ,  John J. Browne ,  Patrick Fleming ,  Tomasz Kantecki ,  John BARRY ,  Patrick Connor

IPC: H04L41/0896 ,  H04L47/762 ,  H04L47/70 ,  G06F11/34 ,  H04L41/5019 ,  H04L49/00 ,  H04L41/0816

CPC classification number: H04L41/0896 ,  H04L47/762 ,  H04L47/822 ,  G06F11/3442 ,  H04L41/5019 ,  H04L49/70 ,  H04L41/0816

Abstract: Technologies for dynamically selecting resources for virtual switching include a computing device configured to identify a present demand on processing resources of the computing device that are configured to process data associated with network packets received by the computing device. Additionally, the computing device is configured to determine a present capacity of one or more acceleration resources of the computing device and configure the virtual switch based on the present demand and the present capacity of the acceleration resources. Other embodiments are described herein.

公开(公告)号：US11703906B2

公开(公告)日：2023-07-18

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US11630693B2

公开(公告)日：2023-04-18

申请号：US15951650

申请日：2018-04-12

Applicant: Intel Corporation

Inventor： John Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Peter McCarthy ,  Liang Ma ,  Mairtin O'Loingsigh ,  Rory Sexton ,  John Griffin ,  Nemanja Marjanovic ,  David Hunt

IPC: G06F9/46 ,  G06F9/48 ,  H04L47/24 ,  G06F1/329 ,  H04L9/40 ,  H04L47/6275 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3234 ,  H04L47/625 ,  G06F9/50 ,  G06F21/60

Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.