中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.017 seconds)

    CAPACITOR INCLUDING MULTILAYER DIELECTRIC STACK
    23.
    发明申请
    CAPACITOR INCLUDING MULTILAYER DIELECTRIC STACK 有权

    公开(公告)号：US20210118983A1

    公开(公告)日：2021-04-22

    申请号：US17116297

    申请日：2020-12-09

    Applicant: INTEL CORPORATION

    Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

    IPC: H01L49/02 ,  H01L23/522

    Abstract: Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed.

    TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE
    24.
    发明申请
    TRANSISTOR GATE TRENCH ENGINEERING TO DECREASE CAPACITANCE AND RESISTANCE 审中-公开

    公开(公告)号：US20200373403A1

    公开(公告)日：2020-11-26

    申请号：US16990219

    申请日：2020-08-11

    Applicant: INTEL CORPORATION

    Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

    Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

    FERROELECTRIC-BASED FIELD-EFFECT TRANSISTOR WITH THRESHOLD VOLTAGE SWITCHING FOR ENHANCED ON-STATE AND OFF-STATE PERFORMANCE
    25.
    发明申请
    FERROELECTRIC-BASED FIELD-EFFECT TRANSISTOR WITH THRESHOLD VOLTAGE SWITCHING FOR ENHANCED ON-STATE AND OFF-STATE PERFORMANCE 审中-公开

    公开(公告)号：US20200321445A1

    公开(公告)日：2020-10-08

    申请号：US16907445

    申请日：2020-06-22

    Applicant: INTEL CORPORATION

    Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

    IPC: H01L29/51 ,  H01L29/20 ,  H01L29/778 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66

    Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on−VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi −Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

    FILM BULK ACOUSTIC RESONATOR (FBAR) RF FILTER HAVING EPITAXIAL LAYERS
    27.
    发明申请
    FILM BULK ACOUSTIC RESONATOR (FBAR) RF FILTER HAVING EPITAXIAL LAYERS 审中-公开

    公开(公告)号：US20190173452A1

    公开(公告)日：2019-06-06

    申请号：US16323665

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： BRUCE A. BLOCK ,  SANSAPTAK DASGUPTA ,  PAUL B. FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

    IPC: H03H9/56 ,  H03H3/02 ,  H03H9/02 ,  H03H9/13 ,  H03H9/17

    Abstract: Techniques are disclosed for forming resonator devices using epitaxially grown piezoelectric films. Given the epitaxy, the films are single crystal or monocrystalline. In some cases, the piezoelectric layer of the resonator device may be an epitaxial III-V layer such as an Aluminum Nitride, Gallium Nitride, or other group III material-nitride (III-N) compound film grown as a part of a single crystal III-V material stack. In an embodiment, the III-V material stack includes, for example, a single crystal AlN layer and a single crystal GaN layer, although any other suitable single crystal piezoelectric materials can be used. An interdigitated transducer (IDT) electrode is provisioned on the piezoelectric layer and defines the operating frequency of the filter. A plurality of the resonator devices can be used to enable filtering specific different frequencies on the same substrate (by varying dimensions of the IDT electrodes).

    TRANSISTORS INCLUDING RETRACTED RAISED SOURCE/DRAIN TO REDUCE PARASITIC CAPACITANCES
    29.
    发明申请
    TRANSISTORS INCLUDING RETRACTED RAISED SOURCE/DRAIN TO REDUCE PARASITIC CAPACITANCES 审中-公开

    公开(公告)号：US20190058042A1

    公开(公告)日：2019-02-21

    申请号：US16080100

    申请日：2016-03-30

    Applicant: INTEL CORPORATION

    Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

    IPC: H01L29/20 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

    Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.

Patent Agency Ranking