公开(公告)号：US20220216065A1

公开(公告)日：2022-07-07

申请号：US17701367

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20190318958A1

公开(公告)日：2019-10-17

申请号：US16317015

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL ,  Rami HOURANI ,  Eungnak HAN

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US20190302615A1

公开(公告)日：2019-10-03

申请号：US16316594

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  James M. BLACKWELL ,  Robert L. BRISTOL ,  Florian GSTREIN

IPC: G03F7/004 ,  G03F7/20

Abstract: A photosensitive composition including metal nanoparticles capped with an organic ligand, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum. A method including synthesizing metal particles including a diameter of 5 nanometers or less, wherein the metal particles includes a metal that absorbs light in the extreme ultraviolet spectrum; and capping the metal particles with an organic ligand. A method including depositing a photosensitive composition on a semiconductor substrate, wherein the photosensitive composition includes metal nanoparticles capped with an organic ligand and the nanoparticles include a metal that absorbs light in the extreme ultraviolet spectrum; exposing the photosensitive composition to light in an ultraviolet spectrum through a mask including a pattern; and transferring the mask pattern to the photosensitive composition.

公开(公告)号：US20190267282A1

公开(公告)日：2019-08-29

申请号：US16346256

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Florian GSTREIN ,  Rami HOURANI ,  Gopinath BHIMARASETTI ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/308 ,  H01L23/528

Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

公开(公告)号：US20180122690A1

公开(公告)日：2018-05-03

申请号：US15573457

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0335 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76897 ,  H01L2224/16225

Abstract: Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.

公开(公告)号：US20170058401A1

公开(公告)日：2017-03-02

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Grant M. KLOSTER ,  Florian GSTREIN ,  Harsono S. SIMKA ,  Paul A. ZIMMERMAN ,  Robert L. BRISTOL

IPC: C23C16/455 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  C23C16/18 ,  C23C16/48

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。