公开(公告)号：US20240030143A1

公开(公告)日：2024-01-25

申请号：US18377183

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/81 ,  H01L24/17 ,  H01L23/5226 ,  H01L24/13 ,  H01L23/53295 ,  H01L24/16 ,  H01L23/49822 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20230138168A1

公开(公告)日：2023-05-04

申请号：US18089542

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220157706A1

公开(公告)日：2022-05-19

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20200373232A1

公开(公告)日：2020-11-26

申请号：US16993112

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20200083645A1

公开(公告)日：2020-03-12

申请号：US16468271

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Jeffrey LEE ,  Brent R. ROTHERMEL ,  Kemal AYGUN

IPC: H01R13/6471 ,  H01R13/6587 ,  H01R43/20

Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.

公开(公告)号：US20190148227A1

公开(公告)日：2019-05-16

申请号：US16098662

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Kemal AYGUN

IPC: H01L21/768 ,  H01L23/50 ,  H01L23/522

Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.

公开(公告)号：US20180331035A1

公开(公告)日：2018-11-15

申请号：US15773896

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Mathew J. MANUSHAROW ,  Kemal AYGUN ,  Mohiuddin MAZUMDER

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H05K1/02 ,  H01R13/6471

Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.

公开(公告)号：US20160088738A1

公开(公告)日：2016-03-24

申请号：US14956214

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Kemal AYGUN ,  Daniel N. SOBIESKI ,  Drew W. DELANEY

IPC: H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K3/007 ,  C23C14/14 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0219 ,  H05K1/185 ,  H05K3/02 ,  H05K3/30 ,  H05K3/4682 ,  H05K2201/0715 ,  H05K2203/1469 ,  H05K2203/308 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.