公开(公告)号：US20240234283A9

公开(公告)日：2024-07-11

申请号：US17968830

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

公开(公告)号：US20240006376A1

公开(公告)日：2024-01-04

申请号：US17857062

申请日：2022-07-04

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06582 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06513

Abstract: A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.

公开(公告)号：US20230187368A1

公开(公告)日：2023-06-15

申请号：US17548628

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/5383 ,  H01L23/5385 ,  H01L21/4857

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

公开(公告)号：US20230065380A1

公开(公告)日：2023-03-02

申请号：US17411062

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

公开(公告)号：US20220068846A1

公开(公告)日：2022-03-03

申请号：US17087667

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Seok Ling LIM ,  Kooi Chi OOI

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01G4/224 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

公开(公告)号：US20180348823A1

公开(公告)日：2018-12-06

申请号：US15778383

申请日：2015-12-10

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng KONG ,  Kooi Chi OOI ,  Bok Eng CHEAH ,  Eng Huat GOH

IPC: G06F1/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

CPC classification number: G06F1/1652 ,  G06F1/163

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.

公开(公告)号：US20170345763A1

公开(公告)日：2017-11-30

申请号：US15505901

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Shanggar PERIAMAN ,  Michael SKINNER ,  Yen Hsiang CHEW ,  Kheng Tat MAR ,  Ridza Effendi ABD RAZAK ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/5387 ,  H01L21/4846 ,  H01L23/3736 ,  H01L23/49572 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2924/15311

Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.