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公开(公告)号:US20180294252A1
公开(公告)日:2018-10-11
申请号:US15766150
申请日:2015-11-05
Applicant: Intel Corporation
Inventor: Bok Eng CHEAH , Jackson Chung Peng KONG , Ping Ping OOI , Kooi Chi OOI , Shanggar PERIAMAN
IPC: H01L25/065 , H01L23/552 , H01L23/00 , H01L25/10 , H01L25/00 , H01L21/56
CPC classification number: H01L25/0657 , H01L21/568 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/552 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/1816 , H01L2924/18162 , H01L2924/00012 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
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公开(公告)号:US20170345763A1
公开(公告)日:2017-11-30
申请号:US15505901
申请日:2014-09-26
Applicant: INTEL CORPORATION
Inventor: Bok Eng CHEAH , Jackson Chung Peng KONG , Shanggar PERIAMAN , Michael SKINNER , Yen Hsiang CHEW , Kheng Tat MAR , Ridza Effendi ABD RAZAK , Kooi Chi OOI
IPC: H01L23/538 , H01L25/065 , H01L21/48
CPC classification number: H01L23/5387 , H01L21/4846 , H01L23/3736 , H01L23/49572 , H01L23/4985 , H01L23/5389 , H01L24/16 , H01L24/18 , H01L24/19 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/24137 , H01L2224/73259 , H01L2924/15311
Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.
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