公开(公告)号：US10998272B2

公开(公告)日：2021-05-04

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed using organic material layers, while allowing for the fabrication of high density interconnects within the electronic interposer without the use of embedded silicon bridges. This is achieved by forming the electronic interposer in three sections, i.e. an upper section, a lower section and a middle section. The middle section may be formed between the upper section and the lower section, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section, and wherein conductive routes within the middle section have a higher density than conductive routes within the upper section and the lower section.

公开(公告)号：US20210098407A1

公开(公告)日：2021-04-01

申请号：US16586158

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US10852495B2

公开(公告)日：2020-12-01

申请号：US15746792

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Sasha N. Oster ,  Gaurav Chawla

IPC: G02B6/42 ,  G06F13/14 ,  H01P5/00 ,  H01Q13/10 ,  H04B1/40 ,  H04B7/00 ,  H04M9/06 ,  G06F13/00

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US20190304931A1

公开(公告)日：2019-10-03

申请号：US16150075

申请日：2018-10-02

Applicant: Intel Corporation

Inventor： Pramod Malatkar ,  Sairam Agraharam ,  Shawna Liff

IPC: H01L23/00 ,  H01L23/13 ,  H01L21/78 ,  H01L29/06 ,  H01L23/498 ,  H05K1/02 ,  H01L21/02

Abstract: Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. An electronic device die is also provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. In addition, an electronic device package is provided that can comprise a substrate having a top surface configured to receive a die and a bottom surface opposing the top surface. The package can also include a die having a top surface and a bottom surface opposing the top surface. The die can be coupled to the top surface of the substrate. The top surface and/or the bottom surface of either the substrate, or the die, or both can have a non-rectangular shaped perimeter.

公开(公告)号：US20170186705A1

公开(公告)日：2017-06-29

申请号：US14757835

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Pramod Malatkar ,  Sairam Agraharam ,  Shawna Liff

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/564 ,  H01L21/02002 ,  H01L21/78 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/80 ,  H01L29/0657 ,  H01L2924/10155 ,  H01L2924/15158 ,  H05K1/02 ,  H05K1/0271 ,  H05K2201/09027

Abstract: Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. An electronic device die is also provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. In addition, an electronic device package is provided that can comprise a substrate having a top surface configured to receive a die and a bottom surface opposing the top surface. The package can also include a die having a top surface and a bottom surface opposing the top surface. The die can be coupled to the top surface of the substrate. The top surface and/or the bottom surface of either the substrate, or the die, or both can have a non-rectangular shaped perimeter.

公开(公告)号：US09635764B2

公开(公告)日：2017-04-25

申请号：US14866648

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shipeng Qiu ,  Shawna Liff ,  Kayleen L Helms ,  Joshua D Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K1/14 ,  H05K3/36 ,  H05K3/22 ,  H05K3/30 ,  H05K3/00

CPC classification number: H05K1/189 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/036 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/22 ,  H05K3/303 ,  H05K3/326 ,  H05K3/361 ,  H05K2201/0133 ,  H05K2201/0308 ,  H05K2201/041 ,  H05K2201/047 ,  H05K2201/057 ,  H05K2201/10007 ,  H05K2201/10128 ,  H05K2203/10 ,  H05K2203/104 ,  H05K2203/105 ,  H05K2203/1105 ,  H05K2203/1194

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

公开(公告)号：US20250112200A1

公开(公告)日：2025-04-03

申请号：US18374559

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Kimin Jun ,  Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Shawna Liff ,  Johanna Swan ,  Michael Baker ,  Bhaskar Jyoti Krishnatreya ,  Chien-An Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

公开(公告)号：US12224261B2

公开(公告)日：2025-02-11

申请号：US17488174

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US12205902B2

公开(公告)日：2025-01-21

申请号：US17388964

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H05K1/18

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US11830831B2

公开(公告)日：2023-11-28

申请号：US16327810

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Johanna Swan ,  Shawna Liff ,  Adel Elsherbini ,  Telesphor Kamgaing ,  Aleksandar Aleksov

IPC: H01L23/66 ,  H01P3/12

CPC classification number: H01L23/66 ,  H01P3/121 ,  H01L2223/6627

Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.