公开(公告)号：US10168760B2

公开(公告)日：2019-01-01

申请号：US15074774

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Anoop Mukker ,  Daniel Nemiroff ,  Nobuyuki Suzuki ,  David W. Vogel

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26

Abstract: An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.

公开(公告)号：US12141356B2

公开(公告)日：2024-11-12

申请号：US17133154

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Deisher ,  Darryl Adams ,  Sylvia Downing ,  Zhenyu Zhu ,  Srikanth Potluri

IPC: G06F3/0488 ,  G06F3/01 ,  G06F3/16 ,  G06F9/4401 ,  G06F9/451 ,  G06N3/04 ,  G06N3/08 ,  G06V10/22 ,  G06V30/262 ,  G10L13/08 ,  G09B21/00

Abstract: Computing platforms and related methods for providing accessible user interfaces are disclosed. An example apparatus includes a display controller to a display controller to sample a region of a display frame associated with a location of a touch on a display screen of a user device and logic circuitry to, after a Basic Input Output System (BIOS) is operational in the user device and prior to loading of an operating system of the user device, identify content in the display region and cause at least one output device to generate an output representative of the content, the output including at least one of an audible output or a haptic output.

公开(公告)号：US11113402B2

公开(公告)日：2021-09-07

申请号：US16370566

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Mark Feuerstraeter ,  Asad Azam ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G05B9/02 ,  G05B19/042

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having a root of trust and an embedded controller to conduct functional safety operations and non-functional safety operations with respect to the SoC. The technology may also include an enhanced serial peripheral interface (eSPI) coupled to the SoC and the embedded controller, wherein the eSPI is to tunnel communications associated with the functional safety operations between the embedded controller and the root of trust.

公开(公告)号：US10860500B2

公开(公告)日：2020-12-08

申请号：US16258828

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Chai Huat Gan

IPC: G06F12/00 ,  G06F12/14 ,  G06F21/60 ,  G06F21/79 ,  G06F21/64 ,  G06F21/10

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

公开(公告)号：US20190129880A1

公开(公告)日：2019-05-02

申请号：US16234081

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Joel L. Finkel ,  Lean Kim Ong ,  Siow Hoay Lim ,  Mikal Hunsaker

IPC: G06F13/40 ,  G06F13/42

Abstract: Apparatuses and methods relating to an enhanced serial peripheral interface (eSPI) port expander circuitry are described. In an embodiment, an apparatus includes an upstream eSPI port, a plurality of downstream eSPI ports, and an eSPI aggregator. The upstream eSPI port is to operate as an eSPI slave on an upstream eSPI bus. Each of the plurality of downstream eSPI ports is to operate as an eSPI master on a corresponding one of a plurality of downstream eSPI buses. The eSPI aggregator is to forward or broadcast transactions from the upstream eSPI bus to one or more of the plurality of downstream eSPI buses and to aggregate responses from one or more of the downstream eSPI buses.

公开(公告)号：US10185696B2

公开(公告)日：2019-01-22

申请号：US15070481

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/00 ,  G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F1/32 ,  G06F9/4401

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

公开(公告)号：US20180293187A1

公开(公告)日：2018-10-11

申请号：US15482646

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Sivakumar Radhakrishnan ,  Mahesh S. Natu ,  Zhenyu Zhu ,  Malay Trivedi ,  Randall L. Albion ,  Chris Ruffin

IPC: G06F13/16 ,  G06F13/24 ,  G06F13/40 ,  G06F3/06 ,  G06F9/44

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0679 ,  G06F13/24 ,  G06F13/4068

Abstract: Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

公开(公告)号：US20180285562A1

公开(公告)日：2018-10-04

申请号：US15476196

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Sivakumar Radhakrishnan ,  Mahesh S. Natu ,  Pawel Szymanski ,  Zhenyu Zhu ,  Malay Trivedi ,  Kirk D. Brannock ,  Geoffrey S. Strongin

IPC: G06F21/55 ,  G11C16/34 ,  G11C16/16 ,  G06F3/06

Abstract: Technology for a computing system is described. The computing system can include memory, a controller, and a security management module. The controller can receive a block erase command for erasing data stored in a block of memory. The controller can store information associated with the block erase command in a store, wherein the information includes a block address associated with the data to be erased based on the block erase command. The security management module can read block addresses from the store, update a block erase count array over a defined interval to include block addresses read from the store, compare the block erase count array to a defined threshold, identify block addresses for which the block erase count array is above the defined threshold, and deny subsequent block erase commands for the identified block addresses.

公开(公告)号：US20170185559A1

公开(公告)日：2017-06-29

申请号：US14998222

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/4068

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

公开(公告)号：US11188492B2

公开(公告)日：2021-11-30

申请号：US16234081

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Joel L. Finkel ,  Lean Kim Ong ,  Siow Hoay Lim ,  Mikal Hunsaker

IPC: G06F13/42 ,  G06F13/40

Abstract: Apparatuses and methods relating to an enhanced serial peripheral interface (eSPI) port expander circuitry are described. In an embodiment, an apparatus includes an upstream eSPI port, a plurality of downstream eSPI ports, and an eSPI aggregator. The upstream eSPI port is to operate as an eSPI slave on an upstream eSPI bus. Each of the plurality of downstream eSPI ports is to operate as an eSPI master on a corresponding one of a plurality of downstream eSPI buses. The eSPI aggregator is to forward or broadcast transactions from the upstream eSPI bus to one or more of the plurality of downstream eSPI buses and to aggregate responses from one or more of the downstream eSPI buses.