公开(公告)号：US20200295132A1

公开(公告)日：2020-09-17

申请号：US16351801

申请日：2019-03-13

Applicant: International Business Machines Corporation

Inventor： Chen ZHANG ,  Peng XU ,  Chun Wing YEUNG

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/786

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

公开(公告)号：US20200013677A1

公开(公告)日：2020-01-09

申请号：US16572743

申请日：2019-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin MIAO ,  Kangguo CHENG ,  Chen ZHANG ,  Wenyu XU

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/423

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

公开(公告)号：US20190096775A1

公开(公告)日：2019-03-28

申请号：US16197692

申请日：2018-11-21

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L21/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/84 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/683

CPC classification number: H01L22/22 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2221/68359

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US20190081157A1

公开(公告)日：2019-03-14

申请号：US16179009

申请日：2018-11-02

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

公开(公告)号：US20180122915A1

公开(公告)日：2018-05-03

申请号：US15856309

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Peng XU ,  Chen ZHANG

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L29/51 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/482 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/785

Abstract: A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.

公开(公告)号：US20180033869A1

公开(公告)日：2018-02-01

申请号：US15726678

申请日：2017-10-06

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Xin MIAO ,  Wenyu XU ,  Chen ZHANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02609 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.