中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

32 records (took 0.018 seconds)

    Integrated circuit pad modeling
    23.
    发明授权
    Integrated circuit pad modeling 有权
    集成电路板建模

    公开(公告)号：US08806415B1

    公开(公告)日：2014-08-12

    申请号：US13768112

    申请日：2013-02-15

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  Kai D. Feng ,  Hailing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F2217/40

    Abstract: A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad.

    Abstract translation: 对集成电路芯片进行建模的方法包括使用在计算机设备上运行的设计工具来生成焊盘的模型。 该方法还包括在模型中的第一节点和第二节点之间串联连接第一电感器，第一电阻器和第一组并联电阻器 - 电感器元件。 该方法还包括在模型中的第二节点和第三节点之间串联连接第二电感器，第二电阻器和第二组并联电阻器 - 电感器元件。 第一个节点对应于接合焊盘的第一个信号端口。 第二节点对应于接合焊盘的第二信号端口。

    ON-CHIP RANDOMNESS GENERATION
    24.
    发明申请
    ON-CHIP RANDOMNESS GENERATION 审中-公开
    片上随机产生

    公开(公告)号：US20140197865A1

    公开(公告)日：2014-07-17

    申请号：US13739151

    申请日：2013-01-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang ,  Emmanuel Yashchin

    IPC: H03K3/313

    CPC classification number: H03K3/84 ,  H03K3/012 ,  H03K3/313 ,  H03K5/01

    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

    Abstract translation: 片上真实噪声发生器，包括具有低电压，高噪声齐纳二极管的嵌入式噪声源和原位闭环齐纳二极管功率控制电路。 本发明提出使用重掺杂多晶硅和硅p-n二极管结构来最小化击穿电压，增加噪声水平和提高可靠性。 本发明还提出了一种原位闭环齐纳二极管控制电路，以保护齐纳二极管免受灾难性烧坏。

    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY
    26.
    发明申请
    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY 有权
    物理不可变的互连功能阵列

    公开(公告)号：US20150348899A1

    公开(公告)日：2015-12-03

    申请号：US14825303

    申请日：2015-08-13

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

    Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

    Clock phase shift detector
    28.
    发明授权
    Clock phase shift detector 有权
    时钟相移检测器

    公开(公告)号：US09077319B2

    公开(公告)日：2015-07-07

    申请号：US14156795

    申请日：2014-01-16

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Jong-ru Guo ,  Trushil N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H03K5/00 ,  H03L7/087

    CPC classification number: H03K5/00 ,  H03L7/087

    Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

    Abstract translation: 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。

    EMBEDDED ON-CHIP SECURITY
    30.
    发明申请
    EMBEDDED ON-CHIP SECURITY 有权
    嵌入式片上安全

    公开(公告)号：US20150084193A1

    公开(公告)日：2015-03-26

    申请号：US14032218

    申请日：2013-09-20

    Applicant: International Business Machines Corporation

    Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC: H01L23/535 ,  H01L23/00 ,  H01L21/768

    CPC classification number: H01L21/76802 ,  G06F21/73 ,  G09C1/00 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/564 ,  H01L23/57 ,  H01L2924/0002 ,  H03K19/003 ,  H03K19/0948 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

    Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

    Abstract translation: 本发明的实施例包括一种半导体结构，其包含用于实现物理不可克隆功能（PUF）的线性随机图案化互连结构的后端，用于形成半导体器件的方法以及用于使互连结构实现物理不可克隆功能的电路 。 该方法包括在衬底上形成半导体衬底和介电层。 随机图案化的互连结构形成在电介质层中。 互连结构的随机图案用于实现物理不可克隆功能，并且是在半导体结构的制造期间发生缺陷的结果。 该电路包括n沟道和p沟道金属氧化物半导体场效应晶体管（MOSFET）和随机图案化的互连结构，其作为MOSFET之间的电连接。 MOSFET之间的随机电气连接用于产生用于诸如认证或识别之类目的的唯一密钥。

Patent Agency Ranking