中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.019 seconds)

    SPIN TRANSFER TORQUE CELL FOR MAGNETIC RANDOM ACCESS MEMORY
    23.
    发明申请
    SPIN TRANSFER TORQUE CELL FOR MAGNETIC RANDOM ACCESS MEMORY 有权
    用于磁性随机存取存储器的转子转矩单元

    公开(公告)号：US20150087080A1

    公开(公告)日：2015-03-26

    申请号：US14556967

    申请日：2014-12-01

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael C. Gaidis ,  Janusz J. Nowak ,  Daniel C. Worledge

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/307 ,  H01L43/08

    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

    Abstract translation: 实施例针对STT MRAM设备。 STT MRAM器件的一个实施例包括参考层，隧道势垒层，自由层和一个或多个导电通孔。 参考层被配置为具有固定的磁矩。 此外，隧道势垒层被配置为使得电子能够通过隧道势垒层在参考层和自由层之间隧穿。 自由层设置在隧道势垒层之下，并被配置为具有用于存储数据的适应性磁矩。 导电通孔设置在自由层下方并连接到电极。 此外，导电通孔的宽度小于自由层的宽度，使得用于存储自由层中的数据的活动STT区域的宽度由导电通孔的宽度限定。

    Linear MRAM device with a self-aligned bottom contact
    25.
    发明授权
    Linear MRAM device with a self-aligned bottom contact 有权
    具有自对准底部触点的线性MRAM器件

    公开(公告)号：US09553257B1

    公开(公告)日：2017-01-24

    申请号：US14949267

    申请日：2015-11-23

    Applicant: International Business Machines Corporation

    Inventor： Anthony J. Annunziata ,  Michael C. Gaidis ,  Rohit Kilaru

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

    Abstract translation: 技术涉及线性磁阻随机存取存储器（MRAM）装置。 线性磁性隧道结结构包括在自由层顶部的非磁性隧道势垒和非磁性隧道势垒顶部的参考层，其中线性磁性隧道结结构处于一条直线上。 底部触点通过柱空间彼此分离，而多个底部触点与线性磁性隧道结结构自对准，使得多个底部触点与线性磁性隧道结结构线并联。 底部触点邻接线性磁隧道结结构的底部。 通过使自由层的非导电部分隔离底部触点和自由层之间的各个界面来形成MRAM器件。 MRAM器件形成在线性磁隧道结结构的线中。

    Injection pillar definition for line MRAM by a self-aligned sidewall transfer
    26.
    发明授权
    Injection pillar definition for line MRAM by a self-aligned sidewall transfer 有权
    注射柱定义通过自对准侧壁转移线MRAM

    公开(公告)号：US09299924B1

    公开(公告)日：2016-03-29

    申请号：US14753163

    申请日：2015-06-29

    Applicant: International Business Machines Corporation

    Inventor： Anthony J. Annunziata ,  Joel D. Chudow ,  Michael C. Gaidis ,  Rohit Kilaru

    IPC: H01L43/12 ,  H01L21/34 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

    CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

    Abstract translation: 技术涉及MRAM系统。 保形膜覆盖形成在上部材料中的沟槽。 上部材料覆盖基板中的导电岛。 选择性地蚀刻保形膜以在沟槽上留下侧壁。 侧壁被蚀刻成垂直的柱，其自对准并且直接位于下面的导电岛的顶部。 将填充材料沉积并平坦化以留下垂直柱的暴露顶部。 MTJ元件形成在填充材料的顶部和垂直柱的暴露的顶部。 将MTJ元件图案化成对应于垂直列的线，并且每条线具有与其中一个垂直列自对准的线MTJ元件。 线路MRAM器件通过将MTJ元件图案化成线。 线路MRAM设备中的每一个分别包括与一个垂直列自对准的线MTJ元件。

    Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction
    27.
    发明授权
    Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction 有权
    基于纳米线磁隧道结中的电流诱导畴壁运动的多位非易失性存储器

    公开(公告)号：US08934289B2

    公开(公告)日：2015-01-13

    申请号：US13689934

    申请日：2012-11-30

    Applicant: International Business Machines Corporation

    Inventor： Anthony J. Annunziata ,  Michael C. Gaidis ,  William Gallagher ,  Luc Thomas

    IPC: G11C11/00 ,  G11C11/16 ,  B82Y99/00

    CPC classification number: G11C11/1675 ,  B82Y99/00 ,  G11C7/1006 ,  G11C11/161 ,  G11C11/5607 ,  G11C19/0808 ,  G11C19/0841 ,  Y10S977/762

    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

    Abstract translation: 提供了一种用于在畴壁纳米线磁性结装置中存储多个位的机制。 基于使用单畴壁的畴壁纳米线磁性结装置的电阻对多个位进行编码。 移动单畴壁以改变畴壁纳米线磁结装置的电阻以编码所选择的位。 检查电阻以确保其对应于所选位的预选电阻。 响应于对应于所选位的预选电阻的电阻，他选择的位被存储。 响应于不是所选位的预选电阻的电阻，单畴壁移动直到电阻对应于预选电阻。

    MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION
    30.
    发明申请
    MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION 有权
    基于NANOWIRE MAGNETIC TUNNEL JUNCTION中的电流感应域墙运动的多位非易失性存储器

    公开(公告)号：US20140126280A1

    公开(公告)日：2014-05-08

    申请号：US13670064

    申请日：2012-11-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony J. Annunziata ,  Michael C. Gaidis ,  William Gallagher ,  Luc Thomas

    IPC: G11C11/16 ,  B82Y99/00

    CPC classification number: G11C11/1675 ,  B82Y99/00 ,  G11C7/1006 ,  G11C11/161 ,  G11C11/5607 ,  G11C19/0808 ,  G11C19/0841 ,  Y10S977/762

    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

    Abstract translation: 提供了一种用于在畴壁纳米线磁性结装置中存储多个位的机制。 基于使用单畴壁的畴壁纳米线磁性结装置的电阻对多个位进行编码。 移动单畴壁以改变畴壁纳米线磁结装置的电阻以编码所选择的位。 检查电阻以确保其对应于所选位的预选电阻。 响应于对应于所选位的预选电阻的电阻，他选择的位被存储。 响应于不是所选位的预选电阻的电阻，单畴壁移动直到电阻对应于预选电阻。

Patent Agency Ranking