公开(公告)号：US10685866B2

公开(公告)日：2020-06-16

申请号：US16126521

申请日：2018-09-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Gen Tsutsui ,  Andrew M. Greene ,  Dechao Guo ,  Huiming Bu ,  Robert Robison ,  Veeraraghavan S. Basker ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66 ,  H01L21/32 ,  H01L29/78

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

公开(公告)号：US11804406B2

公开(公告)日：2023-10-31

申请号：US17383637

申请日：2021-07-23

Applicant: International Business Machines Corporation

Inventor： Christopher J. Penny ,  Brent Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/7684 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5226

Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

公开(公告)号：US20230207387A1

公开(公告)日：2023-06-29

申请号：US17563607

申请日：2021-12-28

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Nicholas Anthony Lanzillo ,  Robert Robison ,  Ruqiang Bao ,  Ardasheir Rahman

IPC: H01L21/768 ,  H01L23/31

CPC classification number: H01L21/76832 ,  H01L23/3192 ,  H01L23/3171 ,  H01L21/76834 ,  H01L21/7682

Abstract: Embodiments of the present disclosure provide a semiconductor structure including a first metal contact, where at least a portion of the first metal contact extends vertically from a substrate to a top portion of the semiconductor structure. The first metal contact having an exposed surface at the top portion of the semiconductor structure. A dielectric cap may be configured around the first metal contact. The dielectric cap is configured to electrically separate a first area of the semiconductor structure from a second area of the semiconductor structure. The first area of the semiconductor structure includes the first metal contact.

公开(公告)号：US11670542B2

公开(公告)日：2023-06-06

申请号：US17570445

申请日：2022-01-07

Applicant: International Business Machines Corporation

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/53295

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

公开(公告)号：US11600565B2

公开(公告)日：2023-03-07

申请号：US17496252

申请日：2021-10-07

Applicant: International Business Machines Corporation

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.

公开(公告)号：US20220199521A1

公开(公告)日：2022-06-23

申请号：US17129971

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Somnath Ghosh ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

公开(公告)号：US11335850B2

公开(公告)日：2022-05-17

申请号：US16816322

申请日：2020-03-12

Applicant: International Business Machines Corporation

Inventor： Karthik Yogendra ,  Robert Robison ,  Eric Raymond Evarts

IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.

公开(公告)号：US11302575B2

公开(公告)日：2022-04-12

申请号：US16941860

申请日：2020-07-29

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Christopher J Penny ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Interconnect structures having subtractive line with damascene second line type are provided. In one aspect, an interconnect structure includes: first metal lines of a first line type disposed on a substrate; and at least one second metal line of a second line type disposed on the substrate between two of the first metal lines, wherein the first line type includes subtractive lines and the second line type includes damascene lines such that the first metal lines have a different metallization structure from the at least one second metal line. A method of forming an interconnect structure is also provided.

公开(公告)号：US20220005732A1

公开(公告)日：2022-01-06

申请号：US17479346

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Brent Anderson ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Robert Robison

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

公开(公告)号：US11195792B2

公开(公告)日：2021-12-07

申请号：US16739556

申请日：2020-01-10

Applicant: International Business Machines Corporation

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.