公开(公告)号：US20140156137A1

公开(公告)日：2014-06-05

申请号：US13689826

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/865

Abstract: An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit.

Abstract translation: 汽车电子系统包括电子控制单元和跟踪适配器。 电子控制单元被配置为接收测量信号并提供控制信号。 此外，电子控制单元被配置为通过用跟踪指令替换二进制图像中的原始指令来生成或提供跟踪信号。 跟踪指令在功能上是等效的，但触发提供跟踪信号。 跟踪适配器耦合到电子控制单元。 跟踪适配器配置为从电子控制单元获取跟踪信号。

公开(公告)号：US20240411667A1

公开(公告)日：2024-12-12

申请号：US18663814

申请日：2024-05-14

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Ibai Irigoyen Ceberio ,  Gasper Skvarc Bozic

IPC: G06F11/36

Abstract: A system and method for tracing a cyclic program execution of a processing circuit of an integrated circuit. A trace unit of the integrated circuit captures trace snippets during respective occurrences of a hyper-period of the cyclic program execution of the processing circuit. A trace buffer of the integrated circuit stores the trace snippets. A processor, which is coupled to the integrated circuit, reconstructs the hyper-period by combining overlapping portions of the trace snippets from the trace buffer.

公开(公告)号：US20200089418A1

公开(公告)日：2020-03-19

申请号：US16690384

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Albrecht Mayer

IPC: G06F3/06 ,  G11C11/56 ,  G06F11/10 ,  G06F11/07

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

公开(公告)号：US10009357B2

公开(公告)日：2018-06-26

申请号：US14728323

申请日：2015-06-02

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Gerd Dirscherl ,  Wieland Fischer

IPC: H04L29/06 ,  H04L29/08 ,  H04L12/40 ,  H04L9/32

CPC classification number: H04L63/12 ,  H04L9/3226 ,  H04L12/40 ,  H04L63/04 ,  H04L63/123 ,  H04L63/126 ,  H04L63/1441 ,  H04L67/10 ,  H04L2012/40273 ,  H04L2209/34

Abstract: A method for generating a data frame is disclosed which contains a user data block with the message and a code block. To generate the code block, a first data record is initially coded by means of a first coding algorithm in order to calculate a first code word. Subsequently, the message is transformed. By using the first code words thus generated and the transformed message, a second code word is subsequently calculated by using a second coding algorithm. The data frame comprises the second code word but not the first code word.

公开(公告)号：US20170322729A1

公开(公告)日：2017-11-09

申请号：US15588973

申请日：2017-05-08

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/1081

Abstract: A method of determining an access address includes determining a first address translation rule to translate a first input address to a first output address, determining a second address translation rule to translate a second input address to a second output address, and using at least one of the first address translation rule and the second address translation rule to determine the access address. An apparatus for accessing a memory based on a memory address includes a first address translator configured to translate a first input address to a first output address and a second address translator configured to translate a second input address to a second output address. The apparatus is configured to use at least one of the first address translator and the second address translator to translate the memory address to the access address.

公开(公告)号：US20170315944A1

公开(公告)日：2017-11-02

申请号：US15140815

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US09612279B2

公开(公告)日：2017-04-04

申请号：US13777132

申请日：2013-02-26

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Simon Brewerton

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/2894 ,  G01R31/3177

Abstract: A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.

公开(公告)号：USRE46021E1

公开(公告)日：2016-05-31

申请号：US13775962

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Albrecht Mayer

IPC: G01R31/28 ,  G06F11/00 ,  G06F11/07 ,  G06F13/18

CPC classification number: G06F11/0724 ,  G06F11/267 ,  G06F13/18

Abstract: A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave debug interface, wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data.

公开(公告)号：US20160042160A1

公开(公告)日：2016-02-11

申请号：US14453116

申请日：2014-08-06

Applicant: Infineon Technologies AG

Inventor： Witold Gora ,  Andreas Geiler ,  Gerd Dirscherl ,  Albrecht Mayer

IPC: G06F21/12 ,  G06F21/14

CPC classification number: G06F21/12 ,  G06F21/14 ,  G06F21/602 ,  G06F2221/0744

Abstract: An apparatus and corresponding method for preventing cloning of code. The apparatus includes a memory, an authentication module, and a device. The memory is configured to store the code, which includes unencrypted code and a fragment of encrypted code. The authentication module is configured to receive and decrypt the fragment of encrypted code from the memory into a fragment of decrypted code, and to store the fragment of decrypted code in an authentication module buffer. The device configured to execute the unencrypted code from the memory and to execute the fragment of decrypted code from the authentication module buffer, wherein the fragment of encrypted code is personalized to the device.

Abstract translation: 一种用于防止代码克隆的装置和相应方法。 该装置包括存储器，认证模块和设备。 存储器被配置为存储代码，其包括未加密的代码和加密代码的片段。 认证模块被配置为将加密代码的片段从存储器接收并解密成解密代码的片段，并将解密的代码片段存储在认证模块缓冲器中。 所述设备被配置为从所述存储器执行未加密的代码并且从所述认证模块缓冲器执行解密代码的片段，其中所述加密代码片段被个性化到所述设备。

公开(公告)号：US20150350241A1

公开(公告)日：2015-12-03

申请号：US14728323

申请日：2015-06-02

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Gerd Dirscherl ,  Wieland Fischer

IPC: H04L29/06 ,  H04L29/08 ,  H04L12/40

CPC classification number: H04L63/12 ,  H04L9/3226 ,  H04L12/40 ,  H04L63/04 ,  H04L63/123 ,  H04L63/126 ,  H04L63/1441 ,  H04L67/10 ,  H04L2012/40273 ,  H04L2209/34

Abstract: A method for generating a data frame is disclosed which contains a user data block with the message and a code block. To generate the code block, a first data record is initially coded by means of a first coding algorithm in order to calculate a first code word. Subsequently, the message is transformed. By using the first code words thus generated and the transformed message, a second code word is subsequently calculated by using a second coding algorithm. The data frame comprises the second code word but not the first code word.

Abstract translation: 公开了一种用于产生数据帧的方法，其包含具有消息的用户数据块和代码块。 为了生成代码块，首先通过第一编码算法对第一数据记录进行编码，以便计算第一代码字。 随后，消息被转换。 通过使用如此生成的第一码字和变换消息，随后通过使用第二编码算法来计算第二码字。 数据帧包括第二码字而不是第一码字。